/**************************************************************************//**
 * @file     N572F072.h
 * @version  V3.0
 * $Revision: 32 $
 * $Date: 14/07/21 11:06a $
 * @brief    N572F072 Series Peripheral Access Layer Header File
 *
 * @note
 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
 *
 ******************************************************************************/



/**
  \mainpage Introduction
  *
  *
  * This user manual describes the usage of N572F072 Series MCU device driver
  *
  * <b>Disclaimer</b>
  *
  * The Software is furnished "AS IS", without warranty as to performance or results, and
  * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
  * warranties, express, implied or otherwise, with regard to the Software, its use, or
  * operation, including without limitation any and all warranties of merchantability, fitness
  * for a particular purpose, and non-infringement of intellectual property rights.
  *
  * <b>Copyright Notice</b>
  *
  * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
  */

/**
  * \page PG_DIR Directory Structure
  * Please refer to Readme.pdf under BSP root directory for the BSP directory structure.
  *
  *
  * \page PG_REV Revision History
  *
  *
  * <b>Revision 3.00.001</b>
  * \li Updated to support new API
*/

#ifndef __N572F072_H__
#define __N572F072_H__

/*
 * ==========================================================================
 * ---------- Interrupt Number Definition -----------------------------------
 * ==========================================================================
*/

/** @addtogroup N572F072_CMSIS N572F072 Device Definitions for CMSIS
  N572F072 Interrupt Number Definition and Configurations for CMSIS
  @{
*/

/**
 * @details  Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
 */
 
typedef	enum IRQn
{
/******	 Cortex-M0 Processor Exceptions	Numbers	***************************************************/
	NonMaskableInt_IRQn		= -14,		/*!< 2 Non Maskable	Interrupt							  */
	HardFault_IRQn			= -13,		/*!< 3 Cortex-M0 Hard Fault	Interrupt					  */
	SVCall_IRQn				= -5,		/*!< 11	Cortex-M0 SV Call Interrupt						  */
	PendSV_IRQn				= -2,		/*!< 14	Cortex-M0 Pend SV Interrupt						  */
	SysTick_IRQn			= -1,		/*!< 15	Cortex-M0 System Tick Interrupt					  */

/******	 N572 specific Interrupt Numbers **********************************************************/
	WDT_IRQn				= 0,
	APU_IRQn				= 1,
	ADC_IRQn				= 2,
	EXINT_IRQn				= 3,
	USBD_IRQn				= 4,
	TMR0_IRQn				= 5,
	TMR1_IRQn				= 6,
	TMR2_IRQn				= 7,
	GPAB_IRQn				= 8,
	SPI0_IRQn				= 9,
	PWM0_IRQn				= 10,
	SPI1_IRQn				= 11,
	TMRF_IRQn				= 12,
	RTC_IRQn				= 13,
	PWRWU_IRQn				= 14
										/*!< maximum of	32 Interrupts are possible				  */
} IRQn_Type;


/*
 * ==========================================================================
 * ----------- Processor and Core Peripheral Section ------------------------
 * ==========================================================================
 */

/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT           0       /*!< armikcmu does not provide a MPU present or not       */
#define __NVIC_PRIO_BITS        2       /*!< armikcmu Supports 2 Bits for the Priority Levels     */
#define __Vendor_SysTickConfig  0       /*!< Set to 1 if different SysTick Config is used         */
/*@}*/ /* end of group N572F072_CMSIS */

#include "core_cm0.h"                   /* Cortex-M0 processor and core peripherals               */
#include "system_N572F072.h"            /* N572F072 System include file                           */

#if defined ( __CC_ARM   )
#pragma anon_unions
#elif  ( defined (__ICCARM__) )
// IAR C compiler detected
  #define __wfi       __WFI
  #ifndef __STATIC_INLINE
    #define __STATIC_INLINE  static inline
  #endif
/*
Usage of #define
  #define A(x)  T_##x
  #define B（x) #@x
  #define C（x) #x

  A(1)------>T_1
  B(1)------>'1'
  C(1)------>"1"
*/
  #define __quote(n)      #n
  #define __iar_align(n)  __quote(data_alignment=##n)
  #define __align(n)      _Pragma(__iar_align(n))
#endif


/******************************************************************************/
/*                Device Specific Peripheral registers structures             */
/******************************************************************************/

/** @addtogroup N572F072_REGISTER N572F072 Control Register

  @{

*/


/*---------------------- Analog to Digital Converter -------------------------*/
/**
    @addtogroup ADC Analog to Digital Converter(ADC)
    Memory Mapped Structure for ADC Controller
@{ */
 
typedef struct
{


    /**
     * DAT0~7
     * ===================================================================================================
     * Offset: 0x00  A/D Data Register for the channel defined in CHSEQn
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:11]  |RESULT    |A/D Conversion Result
     * |        |          |This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit.
     * |[12:15] |EXTS      |Extension Bits Of RESULT For Different Data Format
     * |        |          |If ADCFM is "0", EXTS all are read as "0".
     * |        |          |If ADCFM is "1", EXTS all are read as bit RESULT[11].
     * |[16]    |OV        |Over Run Flag
     * |        |          |1: Data in RESULT are overwritten.
     * |        |          |0: Data in RESULT are recent conversion result.
     * |        |          |If converted data in RESULT have not been read before new conversion result is loaded to this register, OV is set to 1.
     * |        |          |It is cleared by hardware after ADC_DATn register is read.
     * |[17]    |VALID     |Valid Flag
     * |        |          |1: Data in RESULT are valid.
     * |        |          |0: Data in RESULT are not valid.
     * |        |          |This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DATn register is read.
 */
    __I  uint32_t DAT[8];                

    /**
     * CTL
     * ===================================================================================================
     * Offset: 0x20  A/D Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |ADCEN     |A/D Converter Enable
     * |        |          |1: Enable
     * |        |          |0: Disable
     * |        |          |Before starting A/D conversion function, this bit should be set to 1.
     * |        |          |Clear it to 0 to disable A/D converter analog circuit power consumption.
     * |[1]     |ADCIE     |A/D Interrupt Enable
     * |        |          |1: Enable A/D interrupt function
     * |        |          |0: Disable A/D interrupt function
     * |        |          |A/D conversion end interrupt request is generated if ADCIE bit is set to 1.
     * |[2:3]   |OPMODE    |A/D Converter Operation Mode
     * |        |          |00: Single conversion
     * |        |          |01: Reserved
     * |        |          |10: Single-cycle scan
     * |        |          |11: Continuous scan
     * |        |          |When changing the operation mode, software should disable SWTRG bit firstly.
     * |[6:7]   |HWTRGCOND |Trigger Condition
     * |        |          |These two bits decide external pin STADC trigger event is level or edge.
     * |        |          |The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.
     * |        |          |00: Low level
     * |        |          |01: High level
     * |        |          |10: Falling edge
     * |        |          |11: Positive edge
     * |[8]     |HWTRGEN   |Trigger Enable
     * |        |          |Enable or disable triggering of A/D conversion by external STADC pin.
     * |        |          |1= Enable.
     * |        |          |0= Disable.
     * |[11]    |SWTRG     |A/D Conversion Start
     * |        |          |1: Conversion start.
     * |        |          |0: Conversion stopped and A/D converter enter idle state.
     * |        |          |SWTRG bit can be set to 1 from three sources: software write and external pin STADC.
     * |        |          |SWTRG is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel.
     * |        |          |In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets.
     * |[12]    |ADCFM     |Data Format Of ADC Conversion Result
     * |        |          |1: 2'Complemet
     * |        |          |0: Unsigned 
 */
    __IO uint32_t CTL;                  

    /**
     * CHSEQ
     * ===================================================================================================
     * Offset: 0x24  A/D Channel Sequence Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:3]   |CHSEQ0    |Select Channel N As The 1st Conversion In Scan Sequence
     * |        |          |If CHSEQ0[3]=0, one of the following channel is selected according to CHSEQ0[2:0].
     * |        |          |CHSEQ0
     * |        |          |Selected   channel to ADC
     * |        |          |0000
     * |        |          |Channel   0
     * |        |          |0001
     * |        |          |Channel   1
     * |        |          |0010
     * |        |          |Channel   2
     * |        |          |0011
     * |        |          |Channel   3
     * |        |          |0100
     * |        |          |Channel   4
     * |        |          |0101
     * |        |          |Channel   5
     * |        |          |0110
     * |        |          |Channel   6
     * |        |          |0111
     * |        |          |Channel   7
     * |        |          |If CHSEQ0[3]=1,.
     * |        |          | For CHSEQ0[0].=0,.
     * |        |          |Output of pre-amplifier with differential input pair is selected as ADC input.
     * |        |          |The input pair of pre-amplifier is defined in CHSEQ0[2:1].
     * |        |          |CHSEQ0
     * |        |          |Channel   pair to pre-amplifier input
     * |        |          |1000
     * |        |          |Channel   0 and 1
     * |        |          |1010
     * |        |          |Channel   2 and 3
     * |        |          |1100
     * |        |          |Channel   4 and 5
     * |        |          |1110
     * |        |          |None
     * |        |          | For CHSEQ0[0].=1,
     * |        |          | 1xx1: no channel is selected, scan sequence end.
     * |[4:7]   |CHSEQ1    |Select Channel N As The 2nd Conversion In Scan Sequence
     * |        |          |The definition of channel selection is the same as CHSEQ0.
     * |[8:11]  |CHSEQ2    |Select Channel N As The 3rd Conversion In Scan Sequence
     * |        |          |The definition of channel selection is the same as CHSEQ0.
     * |[12:15] |CHSEQ3    |Select Channel N As The 4th Conversion In Scan Sequence
     * |        |          |The definition of channel selection is the same as CHSEQ0.
     * |[16:19] |CHSEQ4    |Select Channel N As The 5th Conversion In Scan Sequence
     * |        |          |The definition of channel selection is the same as CHSEQ0.
     * |[20:23] |CHSEQ5    |Select Channel N As The 6th Conversion In Scan Sequence
     * |        |          |The definition of channel selection is the same as CHSEQ0.
     * |[24:27] |CHSEQ6    |Select Channel N As The 7th Conversion In Scan Sequence
     * |        |          |The definition of channel selection is the same as CHSEQ0.
     * |[28:31] |CHSEQ7    |Select Channel N As The 8th Conversion In Scan Sequence
     * |        |          |The definition of channel selection is the same as CHSEQ0.
 */
    __IO uint32_t CHSEQ;                

    /**
     * CMP0~1
     * ===================================================================================================
     * Offset: 0x28  A/D Compare Register 0, 1
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |ADCMPEN   |Compare Enable
     * |        |          |1: Enable compare.
     * |        |          |0: Disable compare.
     * |        |          |Set this bit to 1 to enable the comparison CMPD with specified channel conversion result when converted data is loaded into ADC_DATn register.
     * |[1]     |ADCMPIE   |Compare Interrupt Enable
     * |        |          |1: Enable
     * |        |          |0: Disable
     * |        |          |When converted data in RESULT is less (or greater) than the compare data CMPD, ADCMPF bit is asserted.
     * |        |          |If ADCMPIE is set to 1, a compare interrupt request is generated.
     * |[2]     |CMPCOND   |Compare Condition
     * |        |          |1: ADCMPFx bit is set if conversion result is greater or equal to CMPD,
     * |        |          |0: ADCMPFx bit is set if conversion result is less than CMPD.
     * |[3:5]   |CMPCH     |Compare Channel Selection
     * |        |          |000: Channel 0 conversion result is selected to be compared.
     * |        |          |001: Channel 1 conversion result is selected to be compared.
     * |        |          |010: Channel 2 conversion result is selected to be compared.
     * |        |          |011: Channel 3 conversion result is selected to be compared.
     * |        |          |100: Channel 4 conversion result is selected to be compared.
     * |        |          |101: Channel 5 conversion result is selected to be compared.
     * |        |          |110: Channel 6 conversion result is selected to be compared.
     * |        |          |111: Channel 7 conversion result is selected to be compared.
     * |[8:11]  |CMPMCNT   |Compare Match Count
     * |        |          |When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1.
     * |        |          |When the internal counter achieves the setting, (CMPMCNT+1) hardware will set the ADCMPF bit.
     * |[16:27] |CMPDAT    |Compare Data
     * |        |          |The 12 bits data are used to compare with conversion result of specified channel.
     * |        |          |Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software.
     * |        |          |The data format should be consistent with the setting of ADCFM bit.
 */
    __IO uint32_t CMP[2];               

    /**
     * STATUS
     * ===================================================================================================
     * Offset: 0x30  A/D Status Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |ADIF      |A/D Conversion Inidcate Flag
     * |        |          |A status flag that indicates the end of A/D conversion.
     * |        |          |ADIF is set to 1 under the following two conditions:
     * |        |          |1. When A/D conversion ends in single mode,
     * |        |          |2. When A/D conversion ends on all channels specified by channel sequence register in scan mode.
     * |        |          |And it is cleared when 1 is written.
     * |[1]     |ADCMPF0   |Compare Flag
     * |        |          |When the selected channel A/D conversion result meets setting conditions in CMP0, then this bit is set to 1.
     * |        |          |And it is cleared by write 1.
     * |        |          |1: Converted result RESULT in ADC_DATn meets CMP0 setting,
     * |        |          |0: Converted result RESULT in ADC_DATn does not meet CMP0 setting.
     * |[2]     |ADCMPF1   |Compare Flag
     * |        |          |When the selected channel A/D conversion result meets setting conditions in CMP1, then this bit is set to 1.
     * |        |          |And it is cleared by write 1.
     * |        |          |1: Converted result RESULT in ADC_DATn meets CMP1 setting,
     * |        |          |0: Converted result RESULT in ADC_DATn does not meet CMP1 setting.
     * |[3]     |BUSY      |BUSY/IDLE
     * |        |          |1: A/D converter is busy at conversion.
     * |        |          |0: A/D converter is in idle state.
     * |        |          |This bit is mirror of SWTRG bit in ADCR.
     * |        |          |It is read only.
     * |[4:6]   |CHANNEL   |Current Conversion Channel
     * |        |          |This filed reflects current conversion channel when BUSY=1.
     * |        |          |When BUSY=0, it shows the next channel will be converted.
     * |        |          |It is read only.
     * |[8:15]  |VALID     |Data Valid Flag
     * |        |          |It is a mirror of VALID bit in ADC_DATn.
     * |[16:23] |OV        |Over Run Flag
     * |        |          |It is a mirror to OV bit in ADC_DATn.
 */
    __IO uint32_t STATUS;                  
         uint32_t RESERVE0[2];


    /**
     * PGCTL
     * ===================================================================================================
     * Offset: 0x3C  ADC Pre-amplifier Gain Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |OPMUTE    |Mute Control Of First Stage Pre-Amp For Offset Bias Calibration
     * |        |          |When this bit set as "1", two input end of first stage pre-amp will be shorted, and feedback resistor of this stage will be shorted.
     * |        |          |0: open
     * |        |          |1: short
     * |[1:2]   |PAG_II    |Gain Setting Bits For The Second Stage Of Pre-Amp
     * |        |          |00: 0 dB,
     * |        |          |01: 10 dB,
     * |        |          |10: 20 dB,
     * |        |          |11: 30 dB.
     * |[8:16]  |OS        |Configuration For Pre-Amp OP Offset Bias Compensation Voltage
     * |        |          |There are 512 levels and 0.25mV per level @ 5V condition.
     * |        |          |The compensation is available only when FWU of MIBSCTL register is 2'b11.
     * |[22]    |MICE      |MIC_BIAS Output Enable
     * |        |          |0: MIC_BIAS output is disabled (tri-state).
     * |        |          |1: MIC_BIAS output is enabled, its output is 0.85 time the voltage of AVDD.
     * |[23]    |APPS      |ADC And Pre-Amplifier Power Source Selection
     * |        |          |0: Internal regulator is disabled, and AVDD is selected as power source.
     * |        |          |1: Internal regulator is enabled, and regulator output is selected as power source.
     * |        |          |The input of internal regulator is from AVDD pin, output of regulator is 0.85 time the voltage of AVDD.
     * |[24:28] |PAG_I     |Gain Setting Bits For The First Stage Of Pre-Amp
     * |        |          |00000: 20 dB,
     * |        |          |00001: 21 dB,
     * |        |          |00010: 22 dB,
     * |        |          |00011: 23 dB,
     * |        |          | :
     * |        |          |10100: 40 dB.
     * |        |          |Others: equivalent with "00000".
 */
    __IO uint32_t PGCTL;                  

    /**
     * MIBSCTL
     * ===================================================================================================
     * Offset: 0x40  MIC bias and PGC Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:1]   |FWU       |Fast Wake Up For RC
     * |        |          |00: 8K (Twu<100ms). set 00 at initial, then 11 after 80ms
     * |        |          |01: 40K
     * |        |          |10: 200K
     * |        |          |11: 400K (Normal path)
     * |[4:5]   |CTRS      |AVDD/2 Accelerating
     * |        |          |00: R~10K
     * |        |          |01: R~40K
     * |        |          |10: R~200K
     * |        |          |11: R~600K
 */
    __IO uint32_t MIBSCTL;                

} ADC_T;

/**
    @addtogroup ADC_CONST ADC Bit Field Definition
    Constant Definitions for ADC Controller
@{ */

#define ADC_DAT_RESULT_Pos            (0)                                         /*!< ADC DAT: RESULT Position              */
#define ADC_DAT_RESULT_Msk            (0xfffful << ADC_DAT_RESULT_Pos)            /*!< ADC DAT: RESULT Mask                  */

#define ADC_DAT_EXTS_Pos              (12)                                        /*!< ADC DAT: EXTS Position              */
#define ADC_DAT_EXTS_Msk              (0xful << ADC_DAT_EXTS_Pos)                 /*!< ADC DAT: EXTS Mask                  */

#define ADC_DAT_OV_Pos                (16)                                        /*!< ADC DAT: OV Position           */
#define ADC_DAT_OV_Msk                (0x1ul << ADC_DAT_OV_Pos)                   /*!< ADC DAT: OV Mask               */

#define ADC_DAT_VALID_Pos             (17)                                        /*!< ADC DAT: VALID Position             */
#define ADC_DAT_VALID_Msk             (0x1ul << ADC_DAT_VALID_Pos)                /*!< ADC DAT: VALID Mask                 */

#define ADC_CTL_ADCEN_Pos             (0)                                         /*!< ADC CTL: ADCEN Position                */
#define ADC_CTL_ADCEN_Msk             (0x1ul << ADC_CTL_ADCEN_Pos)                /*!< ADC CTL: ADCEN Mask                    */

#define ADC_CTL_ADCIE_Pos             (1)                                         /*!< ADC CTL: ADCIE Position                */
#define ADC_CTL_ADCIE_Msk             (0x1ul << ADC_CTL_ADCIE_Pos)                /*!< ADC CTL: ADCIE Mask                    */

#define ADC_CTL_OPMODE_Pos            (2)                                         /*!< ADC CTL: OPMODE Position                */
#define ADC_CTL_OPMODE_Msk            (0x3ul << ADC_CTL_OPMODE_Pos)               /*!< ADC CTL: OPMODE Mask                    */

#define ADC_CTL_HWTRGCOND_Pos         (6)                                         /*!< ADC CTL: HWTRGCOND Position             */
#define ADC_CTL_HWTRGCOND_Msk         (0x3ul << ADC_CTL_HWTRGCOND_Pos)            /*!< ADC CTL: HWTRGCOND Mask                 */

#define ADC_CTL_HWTRGEN_Pos           (8)                                         /*!< ADC CTL: HWTRGEN Position               */
#define ADC_CTL_HWTRGEN_Msk           (0x1ul << ADC_CTL_HWTRGEN_Pos)              /*!< ADC CTL: HWTRGEN Mask                   */

#define ADC_CTL_SWTRG_Pos             (11)                                        /*!< ADC CTL: SWTRG Position                */
#define ADC_CTL_SWTRG_Msk             (0x1ul << ADC_CTL_SWTRG_Pos)                /*!< ADC CTL: SWTRG Mask                    */

#define ADC_CTL_ADCFM_Pos             (12)                                        /*!< ADC CTL: ADCFM Position                */
#define ADC_CTL_ADCFM_Msk             (0x1ul << ADC_CTL_ADCFM_Pos)                /*!< ADC CTL: ADCFM Mask                    */

#define ADC_CHSEQ_CHSEQ0_Pos          (0)                                         /*!< ADC CHSEQ: CHSEQ0 Position             */
#define ADC_CHSEQ_CHSEQ0_Msk          (0xful << ADC_CHSEQ_CHSEQ0_Pos)             /*!< ADC CHSEQ: CHSEQ0 Mask                 */

#define ADC_CHSEQ_CHSEQ1_Pos          (4)                                         /*!< ADC CHSEQ: CHSEQ1 Position             */
#define ADC_CHSEQ_CHSEQ1_Msk          (0xful << ADC_CHSEQ_CHSEQ1_Pos)             /*!< ADC CHSEQ: CHSEQ1 Mask                 */

#define ADC_CHSEQ_CHSEQ2_Pos          (8)                                         /*!< ADC CHSEQ: CHSEQ2 Position             */
#define ADC_CHSEQ_CHSEQ2_Msk          (0xful << ADC_CHSEQ_CHSEQ2_Pos)             /*!< ADC CHSEQ: CHSEQ2 Mask                 */

#define ADC_CHSEQ_CHSEQ3_Pos          (12)                                        /*!< ADC CHSEQ: CHSEQ3 Position             */
#define ADC_CHSEQ_CHSEQ3_Msk          (0xful << ADC_CHSEQ_CHSEQ3_Pos)             /*!< ADC CHSEQ: CHSEQ3 Mask                 */

#define ADC_CHSEQ_CHSEQ4_Pos          (16)                                        /*!< ADC CHSEQ: CHSEQ4 Position             */
#define ADC_CHSEQ_CHSEQ4_Msk          (0xful << ADC_CHSEQ_CHSEQ4_Pos)             /*!< ADC CHSEQ: CHSEQ4 Mask                 */

#define ADC_CHSEQ_CHSEQ5_Pos          (20)                                        /*!< ADC CHSEQ: CHSEQ5 Position             */
#define ADC_CHSEQ_CHSEQ5_Msk          (0xful << ADC_CHSEQ_CHSEQ5_Pos)             /*!< ADC CHSEQ: CHSEQ5 Mask                 */

#define ADC_CHSEQ_CHSEQ6_Pos          (24)                                        /*!< ADC CHSEQ: CHSEQ6 Position             */
#define ADC_CHSEQ_CHSEQ6_Msk          (0xful << ADC_CHSEQ_CHSEQ6_Pos)             /*!< ADC CHSEQ: CHSEQ6 Mask                 */

#define ADC_CHSEQ_CHSEQ7_Pos          (28)                                        /*!< ADC CHSEQ: CHSEQ7 Position             */
#define ADC_CHSEQ_CHSEQ7_Msk          (0xful << ADC_CHSEQ_CHSEQ7_Pos)             /*!< ADC CHSEQ: CHSEQ7 Mask                 */

#define ADC_CMP_ADCMPEN_Pos           (0)                                         /*!< ADC CMP: ADCMPEN Position            */
#define ADC_CMP_ADCMPEN_Msk           (0x1ul << ADC_CMP_ADCMPEN_Pos)              /*!< ADC CMP: ADCMPEN Mask                */

#define ADC_CMP_ADCMPIE_Pos           (1)                                         /*!< ADC CMP: ADCMPIE Position            */
#define ADC_CMP_ADCMPIE_Msk           (0x1ul << ADC_CMP_ADCMPIE_Pos)              /*!< ADC CMP: ADCMPIE Mask                */

#define ADC_CMP_CMPCOND_Pos           (2)                                         /*!< ADC CMP: CMPCOND Position          */
#define ADC_CMP_CMPCOND_Msk           (0x1ul << ADC_CMP_CMPCOND_Pos)              /*!< ADC CMP: CMPCOND Mask              */

#define ADC_CMP_CMPCH_Pos             (3)                                         /*!< ADC CMP: CMPCH Position            */
#define ADC_CMP_CMPCH_Msk             (0x7ul << ADC_CMP_CMPCH_Pos)                /*!< ADC CMP: CMPCH Mask                */

#define ADC_CMP_CMPMCNT_Pos           (8)                                         /*!< ADC CMP: CMPMCNT Position        */
#define ADC_CMP_CMPMCNT_Msk           (0xful << ADC_CMP_CMPMCNT_Pos)              /*!< ADC CMP: CMPMCNT Mask            */

#define ADC_CMP_CMPDAT_Pos            (16)                                        /*!< ADC CMP: CMPDAT Position             */
#define ADC_CMP_CMPDAT_Msk            (0xffful << ADC_CMP_CMPDAT_Pos)             /*!< ADC CMP: CMPDAT Mask                 */

#define ADC_STATUS_ADIF_Pos           (0)                                         /*!< ADC STATUS: ADIF Position                 */
#define ADC_STATUS_ADIF_Msk           (0x1ul << ADC_STATUS_ADIF_Pos)              /*!< ADC STATUS: ADIF Mask                     */

#define ADC_STATUS_ADCMPF0_Pos        (1)                                         /*!< ADC STATUS: ADCMPF0 Position               */
#define ADC_STATUS_ADCMPF0_Msk        (0x1ul << ADC_STATUS_ADCMPF0_Pos)           /*!< ADC STATUS: ADCMPF0 Mask                   */

#define ADC_STATUS_ADCMPF1_Pos        (2)                                         /*!< ADC STATUS: ADCMPF1 Position               */
#define ADC_STATUS_ADCMPF1_Msk        (0x1ul << ADC_STATUS_ADCMPF1_Pos)           /*!< ADC STATUS: ADCMPF1 Mask                   */

#define ADC_STATUS_BUSY_Pos           (3)                                         /*!< ADC STATUS: BUSY Position                */
#define ADC_STATUS_BUSY_Msk           (0x1ul << ADC_STATUS_BUSY_Pos)              /*!< ADC STATUS: BUSY Mask                    */

#define ADC_STATUS_CHANNEL_Pos        (4)                                         /*!< ADC STATUS: CHANNEL Position             */
#define ADC_STATUS_CHANNEL_Msk        (0x7ul << ADC_STATUS_CHANNEL_Pos)           /*!< ADC STATUS: CHANNEL Mask                 */

#define ADC_STATUS_VALID_Pos          (8)                                         /*!< ADC STATUS: VALID Position               */
#define ADC_STATUS_VALID_Msk          (0xfful << ADC_STATUS_VALID_Pos)            /*!< ADC STATUS: VALID Mask                   */

#define ADC_STATUS_OV_Pos             (16)                                        /*!< ADC STATUS: OV Position             */
#define ADC_STATUS_OV_Msk             (0xfful << ADC_STATUS_OV_Pos)               /*!< ADC STATUS: OV Mask                 */

#define ADC_PGCTL_OPMUTE_Pos          (0)                                         /*!< ADC PGCTL: OPMUTE Position              */
#define ADC_PGCTL_OPMUTE_Msk          (0x1ul << ADC_PGCTL_OPMUTE_Pos)             /*!< ADC PGCTL: OPMUTE Mask                  */

#define ADC_PGCTL_PAG_II_Pos          (1)                                         /*!< ADC PGCTL: PAG_II Position              */
#define ADC_PGCTL_PAG_II_Msk          (0x3ul << ADC_PGCTL_PAG_II_Pos)             /*!< ADC PGCTL: PAG_II Mask                  */

#define ADC_PGCTL_OS_Pos              (8)                                         /*!< ADC PGCTL: OS Position                  */
#define ADC_PGCTL_OS_Msk              (0x1fful << ADC_PGCTL_OS_Pos)               /*!< ADC PGCTL: OS Mask                      */

#define ADC_PGCTL_MICE_Pos            (22)                                        /*!< ADC PGCTL: MICE Position                */
#define ADC_PGCTL_MICE_Msk            (0x1ul << ADC_PGCTL_MICE_Pos)               /*!< ADC PGCTL: MICE Mask                    */

#define ADC_PGCTL_APPS_Pos            (23)                                        /*!< ADC PGCTL: APPS Position                */
#define ADC_PGCTL_APPS_Msk            (0x1ul << ADC_PGCTL_APPS_Pos)               /*!< ADC PGCTL: APPS Mask                    */

#define ADC_PGCTL_PAG_I_Pos           (24)                                        /*!< ADC PGCTL: PAG_I Position               */
#define ADC_PGCTL_PAG_I_Msk           (0x1ful << ADC_PGCTL_PAG_I_Pos)             /*!< ADC PGCTL: PAG_I Mask                   */

#define ADC_MIBSCTL_FWU_Pos           (0)                                         /*!< ADC MIBSCTL: FWU Position               */
#define ADC_MIBSCTL_FWU_Msk           (0x3ul << ADC_MIBSCTL_FWU_Pos)              /*!< ADC MIBSCTL: FWU Mask                   */

#define ADC_MIBSCTL_CTRS_Pos         (4)                                          /*!< ADC MIBSCTL: CTRS Position              */
#define ADC_MIBSCTL_CTRS_Msk         (0x3ul << ADC_MIBSCTL_CTRS_Pos)              /*!< ADC MIBSCTL: CTRS Mask                  */

/**@}*/ /* ADC_CONST */
/**@}*/ /* end of ADC register group */


/*---------------------- Audio Process Unit -------------------------*/
/**
    @addtogroup APU Audio Process Unit(APU)
    Memory Mapped Structure for APU Controller
@{ */
 
typedef struct
{


    /**
     * CTL
     * ===================================================================================================
     * Offset: 0x00  APU Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:2]   |TSHD      |APU Interrupt Threshold
     * |        |          |000 = Buffer 0 is read out by APU.
     * |        |          |001 = Buffer 1 is read out by APU.
     * |        |          |010 = Buffer 2 is read out by APU.
     * |        |          |011 = Buffer 3 is read out by APU.
     * |        |          |100 = Buffer 4 is read out by APU.
     * |        |          |101 = Buffer 5 is read out by APU.
     * |        |          |110 = Buffer 6 is read out by APU.
     * |        |          |111 = Buffer 7 is read out by APU.
     * |[5]     |APUIS     |APU Interrupt Status
     * |        |          |0 = APU threshold interrupt does not occur.
     * |        |          |1 = APU threshold interrupt occur.
     * |        |          |This flag is set by hardware when APU threshold is met.
     * |        |          |Software can clear this bit by writing a zero to it.
     * |[6]     |APUIE     |APU Interrupt Enable
     * |        |          |0 = Disable the APU threshold interrupt.
     * |        |          |1 = Enable the APU threshold interrupt.
     * |[7]     |PAMPE     |Power Amplifier Enable
     * |        |          |0 = Disable PA function.
     * |        |          |1 = Enable PA function.
     * |[8]     |DACE      |DAC Enable
     * |        |          |0 = Disable DAC function.
     * |        |          |1 = Enable DAC function.
     * |[9]     |BPPAM     |Bypass Power Amplifier, DAC Output To Pin
     * |        |          |0 = SPK+/DAC pin is one of power amplifier output,.
     * |        |          |1 = SPK+/DAC pin is current DAC output, no output on SPK-.
     * |[13]    |DACGN     |DAC Output Current Control
     * |        |          |0 = 3mA.
     * |        |          |1 = 5mA.
     * |        |          |This bit is effective only when BPPAM is "1". 
 */
    __IO uint32_t CTL;                 

    /**
     * VM
     * ===================================================================================================
     * Offset: 0x04  APU Volume Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:2]   |VOLUM     |APU Volume Adjustment
     * |        |          |000 = 0 dB.
     * |        |          |001 = -3 dB.
     * |        |          |010 = -6 dB.
     * |        |          |011 = -9 dB.
     * |        |          |100 = -12 dB.
     * |        |          |101 = -15 dB.
     * |        |          |110 = -18 dB.
     * |        |          |111 = Reserved.
 */
    __IO uint32_t VM;                 
         uint32_t RESERVE0[1];


    /**
     * CH1DAT
     * ===================================================================================================
     * Offset: 0x0C  APU channel 1 Data Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |PCM1      |PCM Data Of Channel 1
     * |        |          |This field contains 16-bit PCM data that are one of the Mixer input.
     * |        |          |User needs to take care of the effective bit of PCM because the H/W mixer output is clipped to 13 bits automatically.
     * |        |          |The data format of PCM is 2'complement.
 */
    __IO uint32_t CH1DAT;                

    /**
     * CH0DAT0~7
     * ===================================================================================================
     * Offset: 0x10  APU channel 0 Data Register 0~7
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |PCM       |PCM Data Of Channel 0
     * |        |          |This field contains 16-bit PCM data that will be sent to Mixer APU H/W.
     * |        |          |User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.
     * |        |          |The data format of PCM is 2'complement. 
 */
    __IO uint32_t CH0DAT[8];                

} APU_T;

/**
    @addtogroup APU_CONST APU Bit Field Definition
    Constant Definitions for APU Controller
@{ */

#define APU_CTL_TSHD_Pos               (0)                                             /*!< APU CTL: TSHD Position               */
#define APU_CTL_TSHD_Msk               (0x7ul << APU_CTL_TSHD_Pos)                     /*!< APU CTL: TSHD Mask                   */

#define APU_CTL_APUIS_Pos              (5)                                             /*!< APU CTL: APUIS Position              */
#define APU_CTL_APUIS_Msk              (0x1ul << APU_CTL_APUIS_Pos)                    /*!< APU CTL: APUIS Mask                  */

#define APU_CTL_APUIE_Pos              (6)                                             /*!< APU CTL: APUIE Position              */
#define APU_CTL_APUIE_Msk              (0x1ul << APU_CTL_APUIE_Pos)                    /*!< APU CTL: APUIE Mask                  */

#define APU_CTL_PAMPE_Pos              (7)                                             /*!< APU CTL: PAMPE Position              */
#define APU_CTL_PAMPE_Msk              (0x1ul << APU_CTL_PAMPE_Pos)                    /*!< APU CTL: PAMPE Mask                  */

#define APU_CTL_DACE_Pos               (8)                                             /*!< APU CTL: DACE Position               */
#define APU_CTL_DACE_Msk               (0x1ul << APU_CTL_DACE_Pos)                     /*!< APU CTL: DACE Mask                   */

#define APU_CTL_BPPAM_Pos              (9)                                             /*!< APU CTL: BPPAM Position              */
#define APU_CTL_BPPAM_Msk              (0x1ul << APU_CTL_BPPAM_Pos)                    /*!< APU CTL: BPPAM Mask                  */

#define APU_CTL_DACGN_Pos              (13)                                            /*!< APU CTL: DACGN Position              */
#define APU_CTL_DACGN_Msk              (0x1ul << APU_CTL_DACGN_Pos)                    /*!< APU CTL: DACGN Mask                  */

#define APU_VM_VOLUM_Pos               (0)                                             /*!< APU VM: VOLUM Position              */
#define APU_VM_VOLUM_Msk               (0x7ul << APU_VM_VOLUM_Pos)                     /*!< APU VM: VOLUM Mask                  */

#define APU_CH0DAT_PCM_Pos             (0)                                             /*!< APU CH0DAT: PCM Position              */
#define APU_CH0DAT_PCM_Msk             (0xfffful << APU_CH0DAT_PCM_Pos)                /*!< APU CH0DAT: PCM Mask                  */

#define APU_CH1DAT_PCM_Pos             (0)                                             /*!< APU CH1DAT: PCM Position              */
#define APU_CH1DAT_PCM_Msk             (0xfffful << APU_CH1DAT_PCM_Pos)                /*!< APU CH1DAT: PCM Mask                   */

/**@}*/ /* APU_CONST */
/**@}*/ /* end of APU register group */


/*---------------------- System Clock Controller -------------------------*/
/**
    @addtogroup CLK System Clock Controller(CLK)
    Memory Mapped Structure for CLK Controller
@{ */
 
typedef struct
{


    /**
     * PWRCTL
     * ===================================================================================================
     * Offset: 0x00  System Power Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[1]     |XTL32K_EN |External 32.768KHz Crystal Control
     * |        |          |After reset, this bit is "0".
     * |        |          |0 = 32.768KHz Crystal is disabled.
     * |        |          |1 = 32.768KHz Crystal is enabled.
     * |[2]     |OSC48M_EN |Internal 48MHz RC Oscillator Control
     * |        |          |After reset, this bit is "1".
     * |        |          |0 = 48MHz oscillation is disabled.
     * |        |          |1 = 48MHz oscillation is enabled.
     * |[3]     |VOUTX_PD  |Driving Out 3.0V (Through VOUTX Pad) LDO Control
     * |        |          |After reset, this bit is "1".
     * |        |          |0 = 3.0V LDO (VOUTX) is enabled.
     * |        |          |1 = 3.0V LDO (VOUTX) is disabled.
     * |[4]     |WU_DLY    |Enable The Wake Up Delay Counter
     * |        |          |When the chip wakes up from idle mode, the clock control will delay some clock cycles to wait the internal 48MHz oscillator clock stable.
     * |        |          |0 = Disable the clock cycles delay.
     * |        |          |1 = Enable the clock cycles delay, the delay is 512 clock cycles.
     * |[5]     |WINT_EN   |Enable Interrupt When Wake Up From Power Down Mode
     * |        |          |0 = Disable,.
     * |        |          |1 = Enable. The interrupt will occur when MCU wakes up from power down mode
     * |[6]     |WINT_STS  |Chip Power Down Wake Up Status Flag
     * |        |          |Set by "power down wake up", it indicates that resume from power down mode.
     * |        |          |The flag is set if the GPIO, WDT or RTC wakeup.
     * |        |          |Note: Write 1 to clear the bit.
     * |[7]     |PWR_DOWN  |System Power Down Active Or Enable Bit
     * |        |          |To make the programming simple, In order to allow the chip enter power-down mode, both the PWR_DOWN bit and PD_WAIT_CPU bit must be set to 1.
     * |        |          |To reset both PWR_DOWN=0 and PD_WAIT_CPU=0 can make sure the chip operates at normal mode.
     * |        |          |The below truth table summarizes the chip statuses caused by the setting of PWR_DOWN bit and PD_WAIT_CPU bit.
     * |        |          |PD_WAIT_CPU
     * |        |          |PWR_DOWN
     * |        |          |Function
     * |        |          |0
     * |        |          |0
     * |        |          |Chip is at   normal operation.
     * |        |          |0
     * |        |          |1
     * |        |          |This   setting is prohibited.
     * |        |          |The chip will   shut down immediately but may not wake up normally.
     * |        |          |1
     * |        |          |0
     * |        |          |Chip is at   normal operation. This condition exists after the chip wakes up
     * |        |          |1
     * |        |          |1
     * |        |          |This setting   is a prerequisite for entering power-down mode.
     * |        |          |The chip still operates   normally at this stage, but it is already standing by power-down entry   condition.
     * |        |          |The complete   procedure to enter power-down mode is described in below paragraph.
     * |        |          |When both the PD_WAIT_CPU and PWR_DOWN bit are set to "1", the chip still operates normally.
     * |        |          |Until the Cortex_M0 enters sleep state and asserts the signal SLEEPHOLDACKn, then the chip enters the power-down mode.
     * |        |          |When the chip enters the power-down mode and all the chip clocks are disabled, except IP from the 32KHz clock.
     * |        |          |It is suggested to follow the below three steps in order to enter power-down mode.
     * |        |          |The following illustrates the pseudo code for these three steps,.
     * |        |          |Step 1. PWRCON[8]= PD_WAIT_CPU=1 and PWRCON[7]= PWR_DOWN=1.
     * |        |          |Step 2. 0xE000ED10[2]=1.
     * |        |          |Step 3. __wfi()
     * |        |          |When chip wakes up from power down mode, this bit is auto cleared.
     * |        |          |User needs to set this bit again for next power down.
     * |        |          |In power down mode, the internal 48MHz OSC, PLL and all of the AMBA clocks are disabled.
     * |        |          |The 32KHz oscillator is still active if it has been working before entering power-down.
     * |        |          |So the RTC and WDT functions whose clocks are from 32KHz oscillator are active.
     * |        |          |If system wants to avoid interrupt by WDT waking up from power down mode, the WDT should be turned off before entering the power down mode.
     * |        |          |0 = Chip operates at normal mode.
     * |        |          |1 = Chip is standing by power-down entry condition.
     * |[8]     |PD_WAIT_CPU|This Bit Controls The Power Down Entry Condition
     * |        |          |Please refer to PWR_DOWN bit for the usage of PD_WAIT_CPU bit.
     * |        |          |The following is a brief description of PD_WAIT_CPU bit.
     * |        |          |0 = Chip is at normal mode.
     * |        |          |Note that PWR_DOWN cannot be set to 1 when PD_WAIT_CPU value remains at 0, otherwise the chip may not wake up normally.
     * |        |          |1 = Chip waits to enter power-down mode.
 */
    __IO uint32_t PWRCTL;                

    /**
     * AHBCLK
     * ===================================================================================================
     * Offset: 0x04  AHB Device Clock Enable Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[2]     |ISPCKEN   |Flash ISP Engine Clock Enable Control
     * |        |          |0 = To disable the Flash ISP engine clock.
     * |        |          |1 = To enable the Flash ISP engine clock.
     * |[3]     |APUCKEN   |APU Clock Enable Control
     * |        |          |0 = To disable the APU engine clock.
     * |        |          |1 = To enable the APU engine clock.
 */
    __IO uint32_t AHBCLK;                

    /**
     * APBCLK
     * ===================================================================================================
     * Offset: 0x08  APB Device Clock Enable Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |WDT_EN    |Watchdog Clock Enable Control
     * |        |          |This bit is the protected bit.
     * |        |          |To program this bit needs an open lock sequence, write "59h", "16h", "88h" to register SYS_REGLCTL to un-lock this bit.
     * |        |          |Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
     * |        |          |The default bit value is set according to the Flash Controller User Configuration Register CONFIG[31].
     * |        |          |0=Disable.
     * |        |          |1=Enable.
     * |[1]     |RTC_EN    |Real-Time-Clock APB Interface Clock Control
     * |        |          |This bit is used to control the RTC APB clock only.
     * |        |          |The RTC engine clock source is from the 32.768KHz crystal.
     * |        |          |0=Disable.
     * |        |          |1=Enable.
     * |[2]     |TMR0_EN   |Timer0 Clock Enable Control
     * |        |          |0=Disable.
     * |        |          |1=Enable.
     * |[3]     |TMR1_EN   |Timer1 Clock Enable Control
     * |        |          |0=Disable.
     * |        |          |1=Enable.
     * |[4]     |TMR2_EN   |Timer2 Clock Enable Control
     * |        |          |0=Disable.
     * |        |          |1=Enable.
     * |[5]     |TMRF_EN   |TimerF Clock Enable Control
     * |        |          |0=Disable.
     * |        |          |1=Enable.
     * |[12]    |SPI0_EN   |SPI0 Clock Enable Control
     * |        |          |0=Disable.
     * |        |          |1=Enable.
     * |[13]    |SPI1_EN   |SPI1 Clock Enable Control
     * |        |          |0=Disable.
     * |        |          |1=Enable.
     * |[20]    |PWM_EN    |PWM Block Clock Enable Control
     * |        |          |0=Disable.
     * |        |          |1=Enable.
     * |[28]    |ADC_EN    |Audio Analog-Digital-Converter (ADC) Clock Enable Control
     * |        |          |0=Disable.
     * |        |          |1=Enable.
 */
    __IO uint32_t APBCLK;                
         uint32_t RESERVE0[1];


    /**
     * CLKSEL0
     * ===================================================================================================
     * Offset: 0x10  Clock Source Select Control Register 0
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:2]   |HCLKSEL   |HCLK Clock Source Select
     * |        |          |000 = Clock source from XTL_32K.
     * |        |          |010 = Clock source from PLL1_FOUT.
     * |        |          |100 = Clock source from PLL2_FOUT.
     * |        |          |111 = Clock source from RC_48M.
     * |        |          |Others = equivalent with "111".
     * |        |          |Note:
     * |        |          |1. When power on, 48MHz RC is selected as HCLK clock source.
     * |        |          |2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on.
     * |[3:5]   |STCLKSEL  |MCU Cortex_M0 SysTick Clock Source Select
     * |        |          |00 = Clock source from HCLK/2.
     * |        |          |01 = Clock source from XTL_32K.
     * |        |          |1x = Clock source from RC_48M/8.
 */
    __IO uint32_t CLKSEL0;               

    /**
     * CLKSEL1
     * ===================================================================================================
     * Offset: 0x14  Clock Source Select Control Register 1
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:1]   |WDTSEL    |Watchdog Timer Clock Source Selection (Write Protect)
     * |        |          |These bits are protected bits.
     * |        |          |To program these bits needs an open lock sequence, write "59h", "16h", "88h" to SYS_REGLCTL to un-lock these bits.
     * |        |          |Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
     * |        |          |00 = Clock source from HCLK/2048,.
     * |        |          |01 = Clock source from XTL_32K,.
     * |        |          |10 = Clock source from PLL1_FOUT,.
     * |        |          |11 = Clock source from RC_48M/2.
     * |[2:3]   |ADCSEL    |ADC Clock Source Select
     * |        |          |00 = Clock source from PLL2_FOUT,.
     * |        |          |01 = Clock source from HCLK,.
     * |        |          |1x = Clock source from RC_48M.
     * |[4:5]   |SPI0SEL   |SPI0 Clock Source Select
     * |        |          |00 = Clock source from HCLK.
     * |        |          |01 = Clock source from PLL2_FOUT.
     * |        |          |1x = Clock source from RC_48M.
     * |[8:10]  |TMR0SEL   |Timer0 Clock Source Select
     * |        |          |000 = Clock source from HCLK.
     * |        |          |001 = Clock source from XTL_32K.
     * |        |          |010 = Equivalent with "000".
     * |        |          |011 = Clock source from external trigger.
     * |        |          |1xx = Clock source from RC_48M.
     * |[12:14] |TMR1SEL   |Timer1 Clock Source Select
     * |        |          |000 = Clock source from HCLK.
     * |        |          |001 = Clock source from XTL_32K.
     * |        |          |010 = Equivalent with "000".
     * |        |          |011 = Clock source from external trigger.
     * |        |          |1xx = Clock source from RC_48M.
     * |[16:18] |TMR2SEL   |Timer2 Clock Source Select
     * |        |          |000 = Clock source from HCLK.
     * |        |          |001 = Clock source from XTL_32K.
     * |        |          |010 = Equivalent with "000".
     * |        |          |011 = Clock source from external trigger.
     * |        |          |1xx = Clock source from RC_48M.
     * |[20:22] |TMRFSEL   |TimerF Clock Source Select
     * |        |          |000 = Clock source from external XTL_32K/32,.
     * |        |          |001 = Clock source from external XTL_32K/(4x32),.
     * |        |          |110 = Clock source from RC_48M/65536,.
     * |        |          |111 = Clock source from RC_48M/(4x65536),.
     * |        |          |Others = Equivalent with "000".
     * |[28:29] |PWMSEL    |PWM Timer Clock Source Select
     * |        |          |00 = Clock source from HCLK.
     * |        |          |01 = Clock source from XTL_32K.
     * |        |          |10 = Equivalent with "00".
     * |        |          |11 = Clock source from RC_48M.
 */
    __IO uint32_t CLKSEL1;               

    /**
     * CLKDIV
     * ===================================================================================================
     * Offset: 0x18  Clock Divider Number Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:3]   |HCLKDIV   |HCLK Clock Divide Number From HCLK Clock Source
     * |        |          |The HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
     * |[16:23] |ADCDIV    |ADC Clock Divide Number From ADC Clock Source
     * |        |          |The ADC clock frequency ADCLK = (ADC clock source frequency ) / (ADCDIV + 1).
 */
    __IO uint32_t CLKDIV;                
         uint32_t RESERVE1[1];


    /**
     * PLLCON
     * ===================================================================================================
     * Offset: 0x20  PLL Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |PLL2PD    |PLL2 Power Down Mode
     * |        |          |0=Normal Mode
     * |        |          |1=Power Down Mode
     * |[1]     |PLL1PD    |PLL1 Power Down Mode
     * |        |          |0=Normal Mode
     * |        |          |1=Power Down Mode
     * |[2]     |PLL2_SRC  |PLL2 Clock Source Select
     * |        |          |0=RC_48M/8
     * |        |          |1=PLL1_FOUT
     * |[3:4]   |PLL2_FRQ  |PLL2 Output Frequency Select
     * |        |          |00 = 30MHz
     * |        |          |01 = 36MHz
     * |        |          |10 = 42MHz
     * |        |          |11 = 48MHz
 */
         uint32_t PLLCON;                

} CLK_T;

/**
    @addtogroup CLK_CONST CLK Bit Field Definition
    Constant Definitions for CLK Controller
@{ */

#define CLK_PWRCTL_XTL32K_EN_Pos         (1)                                               /*!< CLK PWRCTL: XTL32K_EN Position         */
#define CLK_PWRCTL_XTL32K_EN_Msk         (0x1ul << CLK_PWRCTL_XTL32K_EN_Pos)               /*!< CLK PWRCTL: XTL32K_EN Mask             */

#define CLK_PWRCTL_OSC48M_EN_Pos         (2)                                               /*!< CLK PWRCTL: OSC48M_EN Position         */
#define CLK_PWRCTL_OSC48M_EN_Msk         (0x1ul << CLK_PWRCTL_OSC48M_EN_Pos)               /*!< CLK PWRCTL: OSC48M_EN Mask             */

#define CLK_PWRCTL_VOUTX_PD_Pos          (3)                                               /*!< CLK PWRCTL: VOUTX_PD Position          */
#define CLK_PWRCTL_VOUTX_PD_Msk          (0x1ul << CLK_PWRCTL_VOUTX_PD_Pos)                /*!< CLK PWRCTL: VOUTX_PD Mask              */

#define CLK_PWRCTL_WU_DLY_Pos            (4)                                               /*!< CLK PWRCTL: WU_DLY Position            */
#define CLK_PWRCTL_WU_DLY_Msk            (0x1ul << CLK_PWRCTL_WU_DLY_Pos)                  /*!< CLK PWRCTL: WU_DLY Mask                */

#define CLK_PWRCTL_WINT_EN_Pos           (5)                                               /*!< CLK PWRCTL: WINT_EN Position           */
#define CLK_PWRCTL_WINT_EN_Msk           (0x1ul << CLK_PWRCTL_WINT_EN_Pos)                 /*!< CLK PWRCTL: WINT_EN Mask               */

#define CLK_PWRCTL_WINT_STS_Pos          (6)                                               /*!< CLK PWRCTL: WINT_STS Position          */
#define CLK_PWRCTL_WINT_STS_Msk          (0x1ul << CLK_PWRCTL_WINT_STS_Pos)                /*!< CLK PWRCTL: WINT_STS Mask              */

#define CLK_PWRCTL_PWR_DOWN_Pos          (7)                                               /*!< CLK PWRCTL: PWR_DOWN Position          */
#define CLK_PWRCTL_PWR_DOWN_Msk          (0x1ul << CLK_PWRCTL_PWR_DOWN_Pos)                /*!< CLK PWRCTL: PWR_DOWN Mask              */

#define CLK_PWRCTL_PD_WAIT_CPU_Pos       (8)                                               /*!< CLK PWRCTL: PD_WAIT_CPU Position       */
#define CLK_PWRCTL_PD_WAIT_CPU_Msk       (0x1ul << CLK_PWRCTL_PD_WAIT_CPU_Pos)             /*!< CLK PWRCTL: PD_WAIT_CPU Mask           */

#define CLK_AHBCLK_ISPCKEN_Pos           (2)                                               /*!< CLK AHBCLK: ISPCKEN Position           */
#define CLK_AHBCLK_ISPCKEN_Msk           (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)                 /*!< CLK AHBCLK: ISPCKEN Mask               */

#define CLK_AHBCLK_APUCKEN_Pos           (3)                                               /*!< CLK AHBCLK: APUCKEN Position           */
#define CLK_AHBCLK_APUCKEN_Msk           (0x1ul << CLK_AHBCLK_APUCKEN_Pos)                 /*!< CLK AHBCLK: APUCKEN Mask               */

#define CLK_APBCLK_WDT_EN_Pos            (0)                                               /*!< CLK APBCLK: WDT_EN Position            */
#define CLK_APBCLK_WDT_EN_Msk            (0x1ul << CLK_APBCLK_WDT_EN_Pos)                  /*!< CLK APBCLK: WDT_EN Mask                */

#define CLK_APBCLK_RTC_EN_Pos            (1)                                               /*!< CLK APBCLK: RTC_EN Position            */
#define CLK_APBCLK_RTC_EN_Msk            (0x1ul << CLK_APBCLK_RTC_EN_Pos)                  /*!< CLK APBCLK: RTC_EN Mask                */

#define CLK_APBCLK_TMR0_EN_Pos           (2)                                               /*!< CLK APBCLK: TMR0_EN Position           */
#define CLK_APBCLK_TMR0_EN_Msk           (0x1ul << CLK_APBCLK_TMR0_EN_Pos)                 /*!< CLK APBCLK: TMR0_EN Mask               */

#define CLK_APBCLK_TMR1_EN_Pos           (3)                                               /*!< CLK APBCLK: TMR1_EN Position           */
#define CLK_APBCLK_TMR1_EN_Msk           (0x1ul << CLK_APBCLK_TMR1_EN_Pos)                 /*!< CLK APBCLK: TMR1_EN Mask               */

#define CLK_APBCLK_TMR2_EN_Pos           (4)                                               /*!< CLK APBCLK: TMR2_EN Position           */
#define CLK_APBCLK_TMR2_EN_Msk           (0x1ul << CLK_APBCLK_TMR2_EN_Pos)                 /*!< CLK APBCLK: TMR2_EN Mask               */

#define CLK_APBCLK_TMRF_EN_Pos           (5)                                               /*!< CLK APBCLK: TMRF_EN Position           */
#define CLK_APBCLK_TMRF_EN_Msk           (0x1ul << CLK_APBCLK_TMRF_EN_Pos)                 /*!< CLK APBCLK: TMRF_EN Mask               */

#define CLK_APBCLK_SPI0_EN_Pos           (12)                                              /*!< CLK APBCLK: SPI0_EN Position           */
#define CLK_APBCLK_SPI0_EN_Msk           (0x1ul << CLK_APBCLK_SPI0_EN_Pos)                 /*!< CLK APBCLK: SPI0_EN Mask               */

#define CLK_APBCLK_SPI1_EN_Pos           (13)                                              /*!< CLK APBCLK: SPI1_EN Position           */
#define CLK_APBCLK_SPI1_EN_Msk           (0x1ul << CLK_APBCLK_SPI1_EN_Pos)                 /*!< CLK APBCLK: SPI1_EN Mask               */

#define CLK_APBCLK_PWM_EN_Pos            (20)                                              /*!< CLK APBCLK: PWM_EN Position            */
#define CLK_APBCLK_PWM_EN_Msk            (0x1ul << CLK_APBCLK_PWM_EN_Pos)                  /*!< CLK APBCLK: PWM_EN Mask                */

#define CLK_APBCLK_ADC_EN_Pos            (28)                                              /*!< CLK APBCLK: ADC_EN Position            */
#define CLK_APBCLK_ADC_EN_Msk            (0x1ul << CLK_APBCLK_ADC_EN_Pos)                  /*!< CLK APBCLK: ADC_EN Mask                */

#define CLK_CLKSEL0_HCLKSEL_Pos          (0)                                               /*!< CLK CLKSEL0: HCLKSEL Position          */
#define CLK_CLKSEL0_HCLKSEL_Msk          (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)                /*!< CLK CLKSEL0: HCLKSEL Mask              */

#define CLK_CLKSEL0_STCLKSEL_Pos         (3)                                               /*!< CLK CLKSEL0: STCLKSEL Position         */
#define CLK_CLKSEL0_STCLKSEL_Msk         (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)               /*!< CLK CLKSEL0: STCLKSEL Mask             */

#define CLK_CLKSEL1_WDTSEL_Pos           (0)                                               /*!< CLK CLKSEL1: WDTSEL Position           */
#define CLK_CLKSEL1_WDTSEL_Msk           (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)                 /*!< CLK CLKSEL1: WDTSEL Mask               */

#define CLK_CLKSEL1_ADCSEL_Pos           (2)                                               /*!< CLK CLKSEL1: ADCSEL Position           */
#define CLK_CLKSEL1_ADCSEL_Msk           (0x3ul << CLK_CLKSEL1_ADCSEL_Pos)                 /*!< CLK CLKSEL1: ADCSEL Mask               */

#define CLK_CLKSEL1_SPI0SEL_Pos          (4)                                               /*!< CLK CLKSEL1: SPI0SEL Position          */
#define CLK_CLKSEL1_SPI0SEL_Msk          (0x3ul << CLK_CLKSEL1_SPI0SEL_Pos)                /*!< CLK CLKSEL1: SPI0SEL Mask              */

#define CLK_CLKSEL1_TMR0SEL_Pos          (8)                                               /*!< CLK CLKSEL1: TMR0SEL Position          */
#define CLK_CLKSEL1_TMR0SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)                /*!< CLK CLKSEL1: TMR0SEL Mask              */

#define CLK_CLKSEL1_TMR1SEL_Pos          (12)                                              /*!< CLK CLKSEL1: TMR1SEL Position          */
#define CLK_CLKSEL1_TMR1SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)                /*!< CLK CLKSEL1: TMR1SEL Mask              */

#define CLK_CLKSEL1_TMR2SEL_Pos          (16)                                              /*!< CLK CLKSEL1: TMR2SEL Position          */
#define CLK_CLKSEL1_TMR2SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)                /*!< CLK CLKSEL1: TMR2SEL Mask              */

#define CLK_CLKSEL1_TMRFSEL_Pos          (20)                                              /*!< CLK CLKSEL1: TMRFSEL Position          */
#define CLK_CLKSEL1_TMRFSEL_Msk          (0x7ul << CLK_CLKSEL1_TMRFSEL_Pos)                /*!< CLK CLKSEL1: TMRFSEL Mask              */

#define CLK_CLKSEL1_PWMSEL_Pos           (28)                                              /*!< CLK CLKSEL1: PWMSEL Position           */
#define CLK_CLKSEL1_PWMSEL_Msk           (0x3ul << CLK_CLKSEL1_PWMSEL_Pos)                 /*!< CLK CLKSEL1: PWMSEL Mask               */

#define CLK_CLKDIV_HCLKDIV_Pos           (0)                                               /*!< CLK CLKDIV: HCLKDIV Position           */
#define CLK_CLKDIV_HCLKDIV_Msk           (0xful << CLK_CLKDIV_HCLKDIV_Pos)                 /*!< CLK CLKDIV: HCLKDIV Mask               */

#define CLK_CLKDIV_ADCDIV_Pos            (16)                                              /*!< CLK CLKDIV: ADCDIV Position            */
#define CLK_CLKDIV_ADCDIV_Msk            (0xfful << CLK_CLKDIV_ADCDIV_Pos)                 /*!< CLK CLKDIV: ADCDIV Mask                */

#define CLK_PLLCON_PLL2PD_Pos            (0)                                               /*!< CLK PLLCON: PLL2PD Position         */
#define CLK_PLLCON_PLL2PD_Msk            (0x1ul << CLK_PLLCON_PLL2PD_Pos)                  /*!< CLK PLLCON: PLL2PD Mask             */

#define CLK_PLLCON_PLL1PD_Pos            (1)                                               /*!< CLK PLLCON: PLL1PD Position         */
#define CLK_PLLCON_PLL1PD_Msk            (0x1ul << CLK_PLLCON_PLL1PD_Pos)                  /*!< CLK PLLCON: PLL1PD Mask             */

#define CLK_PLLCON_PLL2_SRC_Pos          (2)                                               /*!< CLK PLLCON: PLL2_SRC Position       */
#define CLK_PLLCON_PLL2_SRC_Msk          (0x1ul << CLK_PLLCON_PLL2_SRC_Pos)                /*!< CLK PWRCTL: PLL2_SRC Mask           */

#define CLK_PLLCON_PLL2_FRQ_Pos          (3)                                               /*!< CLK PLLCON: PLL2_FRQ Position       */
#define CLK_PLLCON_PLL2_FRQ_Msk          (0x3ul << CLK_PLLCON_PLL2_FRQ_Pos)                /*!< CLK PLLCON: PLL2_FRQ Mask           */

/**@}*/ /* CLK_CONST */
/**@}*/ /* end of CLK register group */

/*---------------------- Flash Memory Controller -------------------------*/
/**
    @addtogroup FMC Flash Memory Controller(FMC)
    Memory Mapped Structure for FMC Controller
@{ */
 
typedef struct
{


    /**
     * ISPCTL
     * ===================================================================================================
     * Offset: 0x00  ISP Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |ISPEN     |ISP Enable
     * |        |          |0 = Disable ISP function.
     * |        |          |1 = Enable ISP function.
     * |[1]     |EWEN      |Enable Erase/Write Of ISP Function
     * |        |          |0 = Disable erase/write.
     * |        |          |1 = Enable erase/write.
     * |[4]     |CFGUEN    |CONFIG Update Enable
     * |        |          |0 = Disable.
     * |        |          |1 = Enable.
     * |        |          |When enabled, ISP functions can access the CONFIG address space and modify device configuration area. 
     * |[6]     |ISPFF     |ISP Fail Flag
     * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
     * |        |          |(1) MCU writes (or erase) to Flash when EWEN is "0".
     * |        |          |(2) Destination address is illegal, such as over an available range.
     * |        |          |(3) Destination address is within 0x10000~0x11FFF if PRTB bit of CONFIG is "0".
     * |        |          |(4) Destination address is within 0x00000~0x0FFFF if MOTPB bit of MAP0 is "0".
     * |        |          |(5) Destination address is within 0x10000~0x11FFF if both MOTPB and SOTPB bits of MAP0 are "0".
     * |        |          |Write 1 to clear.
     * |[8:10]  |PT        |Flash Program Time
     * |        |          |000 = 20 ms (default).
     * |        |          |001 = 25 ms.
     * |        |          |010 = 30 ms.
     * |        |          |011 = 35 ms.
     * |        |          |100 = 40 ms.
     * |        |          |101 = 45 ms.
     * |        |          |110 = 10 ms.
     * |        |          |111 = 15 ms.
     * |[12:14] |ET        |Flash Page Erase Time
     * |        |          |000 = 2.0 ms (default).
     * |        |          |001 = 2.5 ms.
     * |        |          |010 = 3.0 ms.
     * |        |          |011 = 1.5 ms.
     * |        |          |100 = 1.0 ms.
     * |        |          |101 = 0.75 ms.
     * |        |          |110 = 4.0 ms.
     * |        |          |111 = 5.0 ms.
 */
    __IO uint32_t ISPCTL;                

    /**
     * ISPADDR
     * ===================================================================================================
     * Offset: 0x04  ISP Address Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:31]  |ISPADDR   |ISP Address Register
     * |        |          |This is the memory address register that a subsequent ISP command will access.
     * |        |          |ISP operation are carried out on 32bit words only, consequently ISPADDR [1:0] must be 00b for correct ISP operation.
     * |        |          |N572F072/P072 equips with an 18Kx32 bits embedded flash.
 */
    __IO uint32_t ISPADDR;               

    /**
     * ISPDAT
     * ===================================================================================================
     * Offset: 0x08  ISP Data Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:31]  |ISPDAT    |ISP Data Register
     * |        |          |Write data to this register before an ISP program operation.
     * |        |          |Read data from this register after an ISP read operation
 */
    __IO uint32_t ISPDAT;                

    /**
     * ISPCMD
     * ===================================================================================================
     * Offset: 0x0C  ISP Command Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:5]   |CMD       |ISP Command
     * |        |          |Operation Mode : CMD
     * |        |          |-------------------- -------
     * |        |          |Standby : 0x3X
     * |        |          |Read CID : 0x0B
     * |        |          |Read DID : 0x0C
     * |        |          |Flash Page Erase : 0x22
     * |        |          |Flash Program : 0x21
     * |        |          |Flash Read : 0x00
 */
    __IO uint32_t ISPCMD;                

    /**
     * ISPTRG
     * ===================================================================================================
     * Offset: 0x10  ISP Trigger Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |ISPGO     |ISP Start Trigger
     * |        |          |Write 1 to start ISP operation.
     * |        |          |This bit will be cleared to 0 by hardware automatically when ISP operation is finished.
     * |        |          |0 = ISP operation is finished.
     * |        |          |1 = ISP is on going.
 */
    __IO uint32_t ISPTRG;                

} FMC_T;

/**
    @addtogroup FMC_CONST FMC Bit Field Definition
    Constant Definitions for FMC Controller
@{ */

#define FMC_ISPCTL_ISPEN_Pos             (0)                                               /*!< FMC ISPCTL: ISPEN Position             */
#define FMC_ISPCTL_ISPEN_Msk             (0x1ul << FMC_ISPCTL_ISPEN_Pos)                   /*!< FMC ISPCTL: ISPEN Mask                 */

#define FMC_ISPCTL_EWEN_Pos              (1)                                               /*!< FMC ISPCTL: EWEN Position              */
#define FMC_ISPCTL_EWEN_Msk              (0x1ul << FMC_ISPCTL_EWEN_Pos)                    /*!< FMC ISPCTL: EWEN Mask                  */

#define FMC_ISPCTL_CFGUEN_Pos            (4)                                               /*!< FMC ISPCTL: CFGUEN Position            */
#define FMC_ISPCTL_CFGUEN_Msk            (0x1ul << FMC_ISPCTL_CFGUEN_Pos)                  /*!< FMC ISPCTL: CFGUEN Mask                */

#define FMC_ISPCTL_ISPFF_Pos             (6)                                               /*!< FMC ISPCTL: ISPFF Position             */
#define FMC_ISPCTL_ISPFF_Msk             (0x1ul << FMC_ISPCTL_ISPFF_Pos)                   /*!< FMC ISPCTL: ISPFF Mask                 */

#define FMC_ISPCTL_PT_Pos                (8)                                               /*!< FMC ISPCTL: PT Position                */
#define FMC_ISPCTL_PT_Msk                (0x7ul << FMC_ISPCTL_PT_Pos)                      /*!< FMC ISPCTL: PT Mask                    */

#define FMC_ISPCTL_ET_Pos                (12)                                              /*!< FMC ISPCTL: ET Position                */
#define FMC_ISPCTL_ET_Msk                (0x7ul << FMC_ISPCTL_ET_Pos)                      /*!< FMC ISPCTL: ET Mask                    */

#define FMC_ISPADDR_ISPADDR_Pos          (0)                                               /*!< FMC ISPADDR: ISPADDR Position          */
#define FMC_ISPADDR_ISPADDR_Msk          (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)         /*!< FMC ISPADDR: ISPADDR Mask              */

#define FMC_ISPDAT_ISPDAT_Pos            (0)                                               /*!< FMC ISPDAT: ISPDAT Position            */
#define FMC_ISPDAT_ISPDAT_Msk            (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)           /*!< FMC ISPDAT: ISPDAT Mask                */

#define FMC_ISPCMD_CMD_Pos               (0)                                               /*!< FMC ISPCMD: CMD Position               */
#define FMC_ISPCMD_CMD_Msk               (0x3ful << FMC_ISPCMD_CMD_Pos)                    /*!< FMC ISPCMD: CMD Mask                   */

#define FMC_ISPTRG_ISPGO_Pos             (0)                                               /*!< FMC ISPTRG: ISPGO Position             */
#define FMC_ISPTRG_ISPGO_Msk             (0x1ul << FMC_ISPTRG_ISPGO_Pos)                   /*!< FMC ISPTRG: ISPGO Mask                 */

/**@}*/ /* FMC_CONST */
/**@}*/ /* end of FMC register group */


/*---------------------- General Purpose Input/Output Controller -------------------------*/
/**
    @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
    Memory Mapped Structure for GPIO Controller
@{ */
 
typedef struct
{


    /**
     * MODE
     * ===================================================================================================
     * Offset: 0x00  GPIO Pin I/O Mode Control
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:1]   |MODE0     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[2:3]   |MODE1     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[4:5]   |MODE2     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[6:7]   |MODE3     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[8:9]   |MODE4     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[10:11] |MODE5     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[12:13] |MODE6     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[14:15] |MODE7     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[16:17] |MODE8     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[18:19] |MODE9     |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[20:21] |MODE10    |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[22:23] |MODE11    |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[24:25] |MODE12    |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[26:27] |MODE13    |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[28:29] |MODE14    |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
     * |[30:31] |MODE15    |Port [A/B] Pin[N] I/O Mode Control
     * |        |          |Determine each I/O type of GPIO Px pins
     * |        |          |00 = GPIO Px[n] pin is in INPUT mode.
     * |        |          |01 = GPIO Px[n] pin is in OUTPUT mode.
     * |        |          |10 = GPIO Px[n] pin is in Open-Drain mode.
     * |        |          |11 = GPIO Px[n] pin is in Quasi-bidirectional mode.
 */
    __IO uint32_t MODE;               

    /**
     * DINOFF
     * ===================================================================================================
     * Offset: 0x04  GPIO Digital Input Path Disable Control
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[16]    |DINOFF0   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[17]    |DINOFF1   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[18]    |DINOFF2   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[19]    |DINOFF3   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[20]    |DINOFF4   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[21]    |DINOFF5   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[22]    |DINOFF6   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[23]    |DINOFF7   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[24]    |DINOFF8   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[25]    |DINOFF9   |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[26]    |DINOFF10  |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[27]    |DINOFF11  |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[28]    |DINOFF12  |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[29]    |DINOFF13  |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[30]    |DINOFF14  |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
     * |[31]    |DINOFF15  |Port [A/B] Pin[N] Digital Input Path Disable Control
     * |        |          |0 = Px.n Digital input path Enable (Default).
     * |        |          |1 = Px.n Digital input path Disable (digital input tied to low). 
 */
    __IO uint32_t DINOFF;             

    /**
     * DOUT
     * ===================================================================================================
     * Offset: 0x08  GPIO Data Output Value
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |DOUT      |Port [A/B] Pin[N] Output Value
     * |        |          |Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
     * |        |          |0 = GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set.
     * |        |          |1 = GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set.
 */
    __IO uint32_t DOUT;               

    /**
     * DATMSK
     * ===================================================================================================
     * Offset: 0x0C  GPIO Data Output Write Mask
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |DATMSK    |Port [A/B] Pin[N] Data Output Write Mask
     * |        |          |These bits are used to protect the corresponding register of Px_DOUT[n].
     * |        |          |When set the DATMSK[n] to "1", the corresponding Px_DOUT[n] bit is writing protected.
     * |        |          |0 = The corresponding Px_DOUT[n] bit can be updated.
     * |        |          |1 = The corresponding Px_DOUT[n] bit is read only.
 */
    __IO uint32_t DATMSK;             

    /**
     * PIN
     * ===================================================================================================
     * Offset: 0x10  GPIO Pin Value
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |PIN       |Port [A/B] Pin[N] Pin Values
     * |        |          |Each bit of the register reflects the actual status of the respective Px.n pin.
     * |        |          |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
 */
    __I  uint32_t PIN;                
         uint32_t RESERVE0[1];


    /**
     * INTTYPE
     * ===================================================================================================
     * Offset: 0x18  GPIO PA Interrupt Trigger Type
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |TYPE      |Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control
     * |        |          |TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered.
     * |        |          |If the interrupt mode is level triggered, the input source is sampled by one HCLK clock to generate the interrupt.
     * |        |          |0 = Edge triggered interrupt.
     * |        |          |1 = Level triggered interrupt.
     * |        |          |Note: If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register.
     * |        |          |If both levels are set, the setting is ignored and no interrupt will occur.
 */
    __IO uint32_t INTTYPE;            

    /**
     * INTEN
     * ===================================================================================================
     * Offset: 0x1C  GPIO Interrupt Enable
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |FLIEN0    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[1]     |FLIEN1    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[2]     |FLIEN2    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[3]     |FLIEN3    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[4]     |FLIEN4    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[5]     |FLIEN5    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[6]     |FLIEN6    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[7]     |FLIEN7    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[8]     |FLIEN8    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[9]     |FLIEN9    |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[10]    |FLIEN10   |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[11]    |FLIEN11   |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[12]    |FLIEN12   |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[13]    |FLIEN13   |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[14]    |FLIEN14   |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[15]    |FLIEN15   |Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
     * |        |          |FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
     * |        |          |0 = Disable Px.n for low-level or high-to-low interrupt.
     * |        |          |1 = Enable Px.n for low-level or high-to-low interrupt.
     * |[16]    |RHIEN0    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[17]    |RHIEN1    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[18]    |RHIEN2    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[19]    |RHIEN3    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[20]    |RHIEN4    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[21]    |RHIEN5    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[22]    |RHIEN6    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[23]    |RHIEN7    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[24]    |RHIEN8    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[25]    |RHIEN9    |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[26]    |RHIEN10   |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[27]    |RHIEN11   |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[28]    |RHIEN12   |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[29]    |RHIEN13   |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[30]    |RHIEN14   |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
     * |[31]    |RHIEN15   |Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
     * |        |          |RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin.
     * |        |          |To set "1" also enables the pin wake-up function.
     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
     * |        |          |If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level.
     * |        |          |If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
     * |        |          |0 = Disable Px.n for low-to-high or level-high interrupt.
     * |        |          |1 = Enable Px.n for low-to-high or level-high interrupt.
 */
    __IO uint32_t INTEN;              

    /**
     * INTSRC
     * ===================================================================================================
     * Offset: 0x20  GPIO Interrupt Source Flag
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |INTSRC    |Port [A/B] Interrupt Source Flag
     * |        |          |Read operation:
     * |        |          |0 = No interrupt from Px.n.
     * |        |          |1 = Px.n generated an interrupt.
     * |        |          |Write operation:
     * |        |          |0 = No action.
     * |        |          |1 = Clear the corresponding pending interrupt.
 */
    __IO uint32_t INTSRC;
} GPIO_T;

/**
    @addtogroup GPIO_CONST GPIO Bit Field Definition
    Constant Definitions for GPIO Controller
@{ */

#define GPIO_MODE_MODE0_Pos              (0)                                               /*!< GPIO MODE: MODE0 Position              */
#define GPIO_MODE_MODE0_Msk              (0x3ul << GPIO_MODE_MODE0_Pos)                    /*!< GPIO MODE: MODE0 Mask                  */

#define GPIO_MODE_MODE1_Pos              (2)                                               /*!< GPIO MODE: MODE1 Position              */
#define GPIO_MODE_MODE1_Msk              (0x3ul << GPIO_MODE_MODE1_Pos)                    /*!< GPIO MODE: MODE1 Mask                  */

#define GPIO_MODE_MODE2_Pos              (4)                                               /*!< GPIO MODE: MODE2 Position              */
#define GPIO_MODE_MODE2_Msk              (0x3ul << GPIO_MODE_MODE2_Pos)                    /*!< GPIO MODE: MODE2 Mask                  */

#define GPIO_MODE_MODE3_Pos              (6)                                               /*!< GPIO MODE: MODE3 Position              */
#define GPIO_MODE_MODE3_Msk              (0x3ul << GPIO_MODE_MODE3_Pos)                    /*!< GPIO MODE: MODE3 Mask                  */

#define GPIO_MODE_MODE4_Pos              (8)                                               /*!< GPIO MODE: MODE4 Position              */
#define GPIO_MODE_MODE4_Msk              (0x3ul << GPIO_MODE_MODE4_Pos)                    /*!< GPIO MODE: MODE4 Mask                  */

#define GPIO_MODE_MODE5_Pos              (10)                                              /*!< GPIO MODE: MODE5 Position              */
#define GPIO_MODE_MODE5_Msk              (0x3ul << GPIO_MODE_MODE5_Pos)                    /*!< GPIO MODE: MODE5 Mask                  */

#define GPIO_MODE_MODE6_Pos              (12)                                              /*!< GPIO MODE: MODE6 Position              */
#define GPIO_MODE_MODE6_Msk              (0x3ul << GPIO_MODE_MODE6_Pos)                    /*!< GPIO MODE: MODE6 Mask                  */

#define GPIO_MODE_MODE7_Pos              (14)                                              /*!< GPIO MODE: MODE7 Position              */
#define GPIO_MODE_MODE7_Msk              (0x3ul << GPIO_MODE_MODE7_Pos)                    /*!< GPIO MODE: MODE7 Mask                  */

#define GPIO_MODE_MODE8_Pos              (16)                                              /*!< GPIO MODE: MODE8 Position              */
#define GPIO_MODE_MODE8_Msk              (0x3ul << GPIO_MODE_MODE8_Pos)                    /*!< GPIO MODE: MODE8 Mask                  */

#define GPIO_MODE_MODE9_Pos              (18)                                              /*!< GPIO MODE: MODE9 Position              */
#define GPIO_MODE_MODE9_Msk              (0x3ul << GPIO_MODE_MODE9_Pos)                    /*!< GPIO MODE: MODE9 Mask                  */

#define GPIO_MODE_MODE10_Pos             (20)                                              /*!< GPIO MODE: MODE10 Position             */
#define GPIO_MODE_MODE10_Msk             (0x3ul << GPIO_MODE_MODE10_Pos)                   /*!< GPIO MODE: MODE10 Mask                 */

#define GPIO_MODE_MODE11_Pos             (22)                                              /*!< GPIO MODE: MODE11 Position             */
#define GPIO_MODE_MODE11_Msk             (0x3ul << GPIO_MODE_MODE11_Pos)                   /*!< GPIO MODE: MODE11 Mask                 */

#define GPIO_MODE_MODE12_Pos             (24)                                              /*!< GPIO MODE: MODE12 Position             */
#define GPIO_MODE_MODE12_Msk             (0x3ul << GPIO_MODE_MODE12_Pos)                   /*!< GPIO MODE: MODE12 Mask                 */

#define GPIO_MODE_MODE13_Pos             (26)                                              /*!< GPIO MODE: MODE13 Position             */
#define GPIO_MODE_MODE13_Msk             (0x3ul << GPIO_MODE_MODE13_Pos)                   /*!< GPIO MODE: MODE13 Mask                 */

#define GPIO_MODE_MODE14_Pos             (28)                                              /*!< GPIO MODE: MODE14 Position             */
#define GPIO_MODE_MODE14_Msk             (0x3ul << GPIO_MODE_MODE14_Pos)                   /*!< GPIO MODE: MODE14 Mask                 */

#define GPIO_MODE_MODE15_Pos             (30)                                              /*!< GPIO MODE: MODE15 Position             */
#define GPIO_MODE_MODE15_Msk             (0x3ul << GPIO_MODE_MODE15_Pos)                   /*!< GPIO MODE: MODE15 Mask                 */

#define GPIO_DINOFF_DINOFF0_Pos          (16)                                              /*!< GPIO DINOFF: DINOFF0 Position          */
#define GPIO_DINOFF_DINOFF0_Msk          (0x1ul << GPIO_DINOFF_DINOFF0_Pos)                /*!< GPIO DINOFF: DINOFF0 Mask              */

#define GPIO_DINOFF_DINOFF1_Pos          (17)                                              /*!< GPIO DINOFF: DINOFF1 Position          */
#define GPIO_DINOFF_DINOFF1_Msk          (0x1ul << GPIO_DINOFF_DINOFF1_Pos)                /*!< GPIO DINOFF: DINOFF1 Mask              */

#define GPIO_DINOFF_DINOFF2_Pos          (18)                                              /*!< GPIO DINOFF: DINOFF2 Position          */
#define GPIO_DINOFF_DINOFF2_Msk          (0x1ul << GPIO_DINOFF_DINOFF2_Pos)                /*!< GPIO DINOFF: DINOFF2 Mask              */

#define GPIO_DINOFF_DINOFF3_Pos          (19)                                              /*!< GPIO DINOFF: DINOFF3 Position          */
#define GPIO_DINOFF_DINOFF3_Msk          (0x1ul << GPIO_DINOFF_DINOFF3_Pos)                /*!< GPIO DINOFF: DINOFF3 Mask              */

#define GPIO_DINOFF_DINOFF4_Pos          (20)                                              /*!< GPIO DINOFF: DINOFF4 Position          */
#define GPIO_DINOFF_DINOFF4_Msk          (0x1ul << GPIO_DINOFF_DINOFF4_Pos)                /*!< GPIO DINOFF: DINOFF4 Mask              */

#define GPIO_DINOFF_DINOFF5_Pos          (21)                                              /*!< GPIO DINOFF: DINOFF5 Position          */
#define GPIO_DINOFF_DINOFF5_Msk          (0x1ul << GPIO_DINOFF_DINOFF5_Pos)                /*!< GPIO DINOFF: DINOFF5 Mask              */

#define GPIO_DINOFF_DINOFF6_Pos          (22)                                              /*!< GPIO DINOFF: DINOFF6 Position          */
#define GPIO_DINOFF_DINOFF6_Msk          (0x1ul << GPIO_DINOFF_DINOFF6_Pos)                /*!< GPIO DINOFF: DINOFF6 Mask              */

#define GPIO_DINOFF_DINOFF7_Pos          (23)                                              /*!< GPIO DINOFF: DINOFF7 Position          */
#define GPIO_DINOFF_DINOFF7_Msk          (0x1ul << GPIO_DINOFF_DINOFF7_Pos)                /*!< GPIO DINOFF: DINOFF7 Mask              */

#define GPIO_DINOFF_DINOFF8_Pos          (24)                                              /*!< GPIO DINOFF: DINOFF8 Position          */
#define GPIO_DINOFF_DINOFF8_Msk          (0x1ul << GPIO_DINOFF_DINOFF8_Pos)                /*!< GPIO DINOFF: DINOFF8 Mask              */

#define GPIO_DINOFF_DINOFF9_Pos          (25)                                              /*!< GPIO DINOFF: DINOFF9 Position          */
#define GPIO_DINOFF_DINOFF9_Msk          (0x1ul << GPIO_DINOFF_DINOFF9_Pos)                /*!< GPIO DINOFF: DINOFF9 Mask              */

#define GPIO_DINOFF_DINOFF10_Pos         (26)                                              /*!< GPIO DINOFF: DINOFF10 Position         */
#define GPIO_DINOFF_DINOFF10_Msk         (0x1ul << GPIO_DINOFF_DINOFF10_Pos)               /*!< GPIO DINOFF: DINOFF10 Mask             */

#define GPIO_DINOFF_DINOFF11_Pos         (27)                                              /*!< GPIO DINOFF: DINOFF11 Position         */
#define GPIO_DINOFF_DINOFF11_Msk         (0x1ul << GPIO_DINOFF_DINOFF11_Pos)               /*!< GPIO DINOFF: DINOFF11 Mask             */

#define GPIO_DINOFF_DINOFF12_Pos         (28)                                              /*!< GPIO DINOFF: DINOFF12 Position         */
#define GPIO_DINOFF_DINOFF12_Msk         (0x1ul << GPIO_DINOFF_DINOFF12_Pos)               /*!< GPIO DINOFF: DINOFF12 Mask             */

#define GPIO_DINOFF_DINOFF13_Pos         (29)                                              /*!< GPIO DINOFF: DINOFF13 Position         */
#define GPIO_DINOFF_DINOFF13_Msk         (0x1ul << GPIO_DINOFF_DINOFF13_Pos)               /*!< GPIO DINOFF: DINOFF13 Mask             */

#define GPIO_DINOFF_DINOFF14_Pos         (30)                                              /*!< GPIO DINOFF: DINOFF14 Position         */
#define GPIO_DINOFF_DINOFF14_Msk         (0x1ul << GPIO_DINOFF_DINOFF14_Pos)               /*!< GPIO DINOFF: DINOFF14 Mask             */

#define GPIO_DINOFF_DINOFF15_Pos         (31)                                              /*!< GPIO DINOFF: DINOFF15 Position         */
#define GPIO_DINOFF_DINOFF15_Msk         (0x1ul << GPIO_DINOFF_DINOFF15_Pos)               /*!< GPIO DINOFF: DINOFF15 Mask             */

#define GPIO_DOUT_DOUT_Pos               (0)                                               /*!< GPIO DOUT: DOUT Position               */
#define GPIO_DOUT_DOUT_Msk               (0xfffful << GPIO_DOUT_DOUT_Pos)                  /*!< GPIO DOUT: DOUT Mask                   */

#define GPIO_DATMSK_DATMSK_Pos           (0)                                               /*!< GPIO DATMSK: DATMSK Position           */
#define GPIO_DATMSK_DATMSK_Msk           (0xfffful << GPIO_DATMSK_DATMSK_Pos)              /*!< GPIO DATMSK: DATMSK Mask               */

#define GPIO_PIN_PIN_Pos                 (0)                                               /*!< GPIO PIN: PIN Position                 */
#define GPIO_PIN_PIN_Msk                 (0xfffful << GPIO_PIN_PIN_Pos)                    /*!< GPIO PIN: PIN Mask                     */

#define GPIO_INTTYPE_TYPE_Pos            (0)                                               /*!< GPIO INTTYPE: TYPE Position            */
#define GPIO_INTTYPE_TYPE_Msk            (0xfffful << GPIO_INTTYPE_TYPE_Pos)               /*!< GPIO INTTYPE: TYPE Mask                */

#define GPIO_INTEN_FLIEN0_Pos            (0)                                               /*!< GPIO INTEN: FLIEN0 Position            */
#define GPIO_INTEN_FLIEN0_Msk            (0x1ul << GPIO_INTEN_FLIEN0_Pos)                  /*!< GPIO INTEN: FLIEN0 Mask                */

#define GPIO_INTEN_FLIEN1_Pos            (1)                                               /*!< GPIO INTEN: FLIEN1 Position            */
#define GPIO_INTEN_FLIEN1_Msk            (0x1ul << GPIO_INTEN_FLIEN1_Pos)                  /*!< GPIO INTEN: FLIEN1 Mask                */

#define GPIO_INTEN_FLIEN2_Pos            (2)                                               /*!< GPIO INTEN: FLIEN2 Position            */
#define GPIO_INTEN_FLIEN2_Msk            (0x1ul << GPIO_INTEN_FLIEN2_Pos)                  /*!< GPIO INTEN: FLIEN2 Mask                */

#define GPIO_INTEN_FLIEN3_Pos            (3)                                               /*!< GPIO INTEN: FLIEN3 Position            */
#define GPIO_INTEN_FLIEN3_Msk            (0x1ul << GPIO_INTEN_FLIEN3_Pos)                  /*!< GPIO INTEN: FLIEN3 Mask                */

#define GPIO_INTEN_FLIEN4_Pos            (4)                                               /*!< GPIO INTEN: FLIEN4 Position            */
#define GPIO_INTEN_FLIEN4_Msk            (0x1ul << GPIO_INTEN_FLIEN4_Pos)                  /*!< GPIO INTEN: FLIEN4 Mask                */

#define GPIO_INTEN_FLIEN5_Pos            (5)                                               /*!< GPIO INTEN: FLIEN5 Position            */
#define GPIO_INTEN_FLIEN5_Msk            (0x1ul << GPIO_INTEN_FLIEN5_Pos)                  /*!< GPIO INTEN: FLIEN5 Mask                */

#define GPIO_INTEN_FLIEN6_Pos            (6)                                               /*!< GPIO INTEN: FLIEN6 Position            */
#define GPIO_INTEN_FLIEN6_Msk            (0x1ul << GPIO_INTEN_FLIEN6_Pos)                  /*!< GPIO INTEN: FLIEN6 Mask                */

#define GPIO_INTEN_FLIEN7_Pos            (7)                                               /*!< GPIO INTEN: FLIEN7 Position            */
#define GPIO_INTEN_FLIEN7_Msk            (0x1ul << GPIO_INTEN_FLIEN7_Pos)                  /*!< GPIO INTEN: FLIEN7 Mask                */

#define GPIO_INTEN_FLIEN8_Pos            (8)                                               /*!< GPIO INTEN: FLIEN8 Position            */
#define GPIO_INTEN_FLIEN8_Msk            (0x1ul << GPIO_INTEN_FLIEN8_Pos)                  /*!< GPIO INTEN: FLIEN8 Mask                */

#define GPIO_INTEN_FLIEN9_Pos            (9)                                               /*!< GPIO INTEN: FLIEN9 Position            */
#define GPIO_INTEN_FLIEN9_Msk            (0x1ul << GPIO_INTEN_FLIEN9_Pos)                  /*!< GPIO INTEN: FLIEN9 Mask                */

#define GPIO_INTEN_FLIEN10_Pos           (10)                                              /*!< GPIO INTEN: FLIEN10 Position           */
#define GPIO_INTEN_FLIEN10_Msk           (0x1ul << GPIO_INTEN_FLIEN10_Pos)                 /*!< GPIO INTEN: FLIEN10 Mask               */

#define GPIO_INTEN_FLIEN11_Pos           (11)                                              /*!< GPIO INTEN: FLIEN11 Position           */
#define GPIO_INTEN_FLIEN11_Msk           (0x1ul << GPIO_INTEN_FLIEN11_Pos)                 /*!< GPIO INTEN: FLIEN11 Mask               */

#define GPIO_INTEN_FLIEN12_Pos           (12)                                              /*!< GPIO INTEN: FLIEN12 Position           */
#define GPIO_INTEN_FLIEN12_Msk           (0x1ul << GPIO_INTEN_FLIEN12_Pos)                 /*!< GPIO INTEN: FLIEN12 Mask               */

#define GPIO_INTEN_FLIEN13_Pos           (13)                                              /*!< GPIO INTEN: FLIEN13 Position           */
#define GPIO_INTEN_FLIEN13_Msk           (0x1ul << GPIO_INTEN_FLIEN13_Pos)                 /*!< GPIO INTEN: FLIEN13 Mask               */

#define GPIO_INTEN_FLIEN14_Pos           (14)                                              /*!< GPIO INTEN: FLIEN14 Position           */
#define GPIO_INTEN_FLIEN14_Msk           (0x1ul << GPIO_INTEN_FLIEN14_Pos)                 /*!< GPIO INTEN: FLIEN14 Mask               */

#define GPIO_INTEN_FLIEN15_Pos           (15)                                              /*!< GPIO INTEN: FLIEN15 Position           */
#define GPIO_INTEN_FLIEN15_Msk           (0x1ul << GPIO_INTEN_FLIEN15_Pos)                 /*!< GPIO INTEN: FLIEN15 Mask               */

#define GPIO_INTEN_RHIEN0_Pos            (16)                                              /*!< GPIO INTEN: RHIEN0 Position            */
#define GPIO_INTEN_RHIEN0_Msk            (0x1ul << GPIO_INTEN_RHIEN0_Pos)                  /*!< GPIO INTEN: RHIEN0 Mask                */

#define GPIO_INTEN_RHIEN1_Pos            (17)                                              /*!< GPIO INTEN: RHIEN1 Position            */
#define GPIO_INTEN_RHIEN1_Msk            (0x1ul << GPIO_INTEN_RHIEN1_Pos)                  /*!< GPIO INTEN: RHIEN1 Mask                */

#define GPIO_INTEN_RHIEN2_Pos            (18)                                              /*!< GPIO INTEN: RHIEN2 Position            */
#define GPIO_INTEN_RHIEN2_Msk            (0x1ul << GPIO_INTEN_RHIEN2_Pos)                  /*!< GPIO INTEN: RHIEN2 Mask                */

#define GPIO_INTEN_RHIEN3_Pos            (19)                                              /*!< GPIO INTEN: RHIEN3 Position            */
#define GPIO_INTEN_RHIEN3_Msk            (0x1ul << GPIO_INTEN_RHIEN3_Pos)                  /*!< GPIO INTEN: RHIEN3 Mask                */

#define GPIO_INTEN_RHIEN4_Pos            (20)                                              /*!< GPIO INTEN: RHIEN4 Position            */
#define GPIO_INTEN_RHIEN4_Msk            (0x1ul << GPIO_INTEN_RHIEN4_Pos)                  /*!< GPIO INTEN: RHIEN4 Mask                */

#define GPIO_INTEN_RHIEN5_Pos            (21)                                              /*!< GPIO INTEN: RHIEN5 Position            */
#define GPIO_INTEN_RHIEN5_Msk            (0x1ul << GPIO_INTEN_RHIEN5_Pos)                  /*!< GPIO INTEN: RHIEN5 Mask                */

#define GPIO_INTEN_RHIEN6_Pos            (22)                                              /*!< GPIO INTEN: RHIEN6 Position            */
#define GPIO_INTEN_RHIEN6_Msk            (0x1ul << GPIO_INTEN_RHIEN6_Pos)                  /*!< GPIO INTEN: RHIEN6 Mask                */

#define GPIO_INTEN_RHIEN7_Pos            (23)                                              /*!< GPIO INTEN: RHIEN7 Position            */
#define GPIO_INTEN_RHIEN7_Msk            (0x1ul << GPIO_INTEN_RHIEN7_Pos)                  /*!< GPIO INTEN: RHIEN7 Mask                */

#define GPIO_INTEN_RHIEN8_Pos            (24)                                              /*!< GPIO INTEN: RHIEN8 Position            */
#define GPIO_INTEN_RHIEN8_Msk            (0x1ul << GPIO_INTEN_RHIEN8_Pos)                  /*!< GPIO INTEN: RHIEN8 Mask                */

#define GPIO_INTEN_RHIEN9_Pos            (25)                                              /*!< GPIO INTEN: RHIEN9 Position            */
#define GPIO_INTEN_RHIEN9_Msk            (0x1ul << GPIO_INTEN_RHIEN9_Pos)                  /*!< GPIO INTEN: RHIEN9 Mask                */

#define GPIO_INTEN_RHIEN10_Pos           (26)                                              /*!< GPIO INTEN: RHIEN10 Position           */
#define GPIO_INTEN_RHIEN10_Msk           (0x1ul << GPIO_INTEN_RHIEN10_Pos)                 /*!< GPIO INTEN: RHIEN10 Mask               */

#define GPIO_INTEN_RHIEN11_Pos           (27)                                              /*!< GPIO INTEN: RHIEN11 Position           */
#define GPIO_INTEN_RHIEN11_Msk           (0x1ul << GPIO_INTEN_RHIEN11_Pos)                 /*!< GPIO INTEN: RHIEN11 Mask               */

#define GPIO_INTEN_RHIEN12_Pos           (28)                                              /*!< GPIO INTEN: RHIEN12 Position           */
#define GPIO_INTEN_RHIEN12_Msk           (0x1ul << GPIO_INTEN_RHIEN12_Pos)                 /*!< GPIO INTEN: RHIEN12 Mask               */

#define GPIO_INTEN_RHIEN13_Pos           (29)                                              /*!< GPIO INTEN: RHIEN13 Position           */
#define GPIO_INTEN_RHIEN13_Msk           (0x1ul << GPIO_INTEN_RHIEN13_Pos)                 /*!< GPIO INTEN: RHIEN13 Mask               */

#define GPIO_INTEN_RHIEN14_Pos           (30)                                              /*!< GPIO INTEN: RHIEN14 Position           */
#define GPIO_INTEN_RHIEN14_Msk           (0x1ul << GPIO_INTEN_RHIEN14_Pos)                 /*!< GPIO INTEN: RHIEN14 Mask               */

#define GPIO_INTEN_RHIEN15_Pos           (31)                                              /*!< GPIO INTEN: RHIEN15 Position           */
#define GPIO_INTEN_RHIEN15_Msk           (0x1ul << GPIO_INTEN_RHIEN15_Pos)                 /*!< GPIO INTEN: RHIEN15 Mask               */

#define GPIO_INTSRC_INTSRC_Pos           (0)                                               /*!< GPIO INTSRC: INTSRC Position           */
#define GPIO_INTSRC_INTSRC_Msk           (0xfffful << GPIO_INTSRC_INTSRC_Pos)              /*!< GPIO INTSRC: INTSRC Mask               */

#define GPIO_MODE_MODE0_Pos              (0)                                               /*!< GPIO MODE: MODE0 Position              */
#define GPIO_MODE_MODE0_Msk              (0x3ul << GPIO_MODE_MODE0_Pos)                    /*!< GPIO MODE: MODE0 Mask                  */

#define GPIO_MODE_MODE1_Pos              (2)                                               /*!< GPIO MODE: MODE1 Position              */
#define GPIO_MODE_MODE1_Msk              (0x3ul << GPIO_MODE_MODE1_Pos)                    /*!< GPIO MODE: MODE1 Mask                  */

#define GPIO_MODE_MODE2_Pos              (4)                                               /*!< GPIO MODE: MODE2 Position              */
#define GPIO_MODE_MODE2_Msk              (0x3ul << GPIO_MODE_MODE2_Pos)                    /*!< GPIO MODE: MODE2 Mask                  */

#define GPIO_MODE_MODE3_Pos              (6)                                               /*!< GPIO MODE: MODE3 Position              */
#define GPIO_MODE_MODE3_Msk              (0x3ul << GPIO_MODE_MODE3_Pos)                    /*!< GPIO MODE: MODE3 Mask                  */

#define GPIO_MODE_MODE4_Pos              (8)                                               /*!< GPIO MODE: MODE4 Position              */
#define GPIO_MODE_MODE4_Msk              (0x3ul << GPIO_MODE_MODE4_Pos)                    /*!< GPIO MODE: MODE4 Mask                  */

#define GPIO_MODE_MODE5_Pos              (10)                                              /*!< GPIO MODE: MODE5 Position              */
#define GPIO_MODE_MODE5_Msk              (0x3ul << GPIO_MODE_MODE5_Pos)                    /*!< GPIO MODE: MODE5 Mask                  */

#define GPIO_MODE_MODE6_Pos              (12)                                              /*!< GPIO MODE: MODE6 Position              */
#define GPIO_MODE_MODE6_Msk              (0x3ul << GPIO_MODE_MODE6_Pos)                    /*!< GPIO MODE: MODE6 Mask                  */

#define GPIO_MODE_MODE7_Pos              (14)                                              /*!< GPIO MODE: MODE7 Position              */
#define GPIO_MODE_MODE7_Msk              (0x3ul << GPIO_MODE_MODE7_Pos)                    /*!< GPIO MODE: MODE7 Mask                  */

#define GPIO_MODE_MODE8_Pos              (16)                                              /*!< GPIO MODE: MODE8 Position              */
#define GPIO_MODE_MODE8_Msk              (0x3ul << GPIO_MODE_MODE8_Pos)                    /*!< GPIO MODE: MODE8 Mask                  */

#define GPIO_MODE_MODE9_Pos              (18)                                              /*!< GPIO MODE: MODE9 Position              */
#define GPIO_MODE_MODE9_Msk              (0x3ul << GPIO_MODE_MODE9_Pos)                    /*!< GPIO MODE: MODE9 Mask                  */

#define GPIO_MODE_MODE10_Pos             (20)                                              /*!< GPIO MODE: MODE10 Position             */
#define GPIO_MODE_MODE10_Msk             (0x3ul << GPIO_MODE_MODE10_Pos)                   /*!< GPIO MODE: MODE10 Mask                 */

#define GPIO_MODE_MODE11_Pos             (22)                                              /*!< GPIO MODE: MODE11 Position             */
#define GPIO_MODE_MODE11_Msk             (0x3ul << GPIO_MODE_MODE11_Pos)                   /*!< GPIO MODE: MODE11 Mask                 */

#define GPIO_MODE_MODE12_Pos             (24)                                              /*!< GPIO MODE: MODE12 Position             */
#define GPIO_MODE_MODE12_Msk             (0x3ul << GPIO_MODE_MODE12_Pos)                   /*!< GPIO MODE: MODE12 Mask                 */

#define GPIO_MODE_MODE13_Pos             (26)                                              /*!< GPIO MODE: MODE13 Position             */
#define GPIO_MODE_MODE13_Msk             (0x3ul << GPIO_MODE_MODE13_Pos)                   /*!< GPIO MODE: MODE13 Mask                 */

#define GPIO_MODE_MODE14_Pos             (28)                                              /*!< GPIO MODE: MODE14 Position             */
#define GPIO_MODE_MODE14_Msk             (0x3ul << GPIO_MODE_MODE14_Pos)                   /*!< GPIO MODE: MODE14 Mask                 */

#define GPIO_MODE_MODE15_Pos             (30)                                              /*!< GPIO MODE: MODE15 Position             */
#define GPIO_MODE_MODE15_Msk             (0x3ul << GPIO_MODE_MODE15_Pos)                   /*!< GPIO MODE: MODE15 Mask                 */

#define GPIO_DINOFF_DINOFF0_Pos          (16)                                              /*!< GPIO DINOFF: DINOFF0 Position          */
#define GPIO_DINOFF_DINOFF0_Msk          (0x1ul << GPIO_DINOFF_DINOFF0_Pos)                /*!< GPIO DINOFF: DINOFF0 Mask              */

#define GPIO_DINOFF_DINOFF1_Pos          (17)                                              /*!< GPIO DINOFF: DINOFF1 Position          */
#define GPIO_DINOFF_DINOFF1_Msk          (0x1ul << GPIO_DINOFF_DINOFF1_Pos)                /*!< GPIO DINOFF: DINOFF1 Mask              */

#define GPIO_DINOFF_DINOFF2_Pos          (18)                                              /*!< GPIO DINOFF: DINOFF2 Position          */
#define GPIO_DINOFF_DINOFF2_Msk          (0x1ul << GPIO_DINOFF_DINOFF2_Pos)                /*!< GPIO DINOFF: DINOFF2 Mask              */

#define GPIO_DINOFF_DINOFF3_Pos          (19)                                              /*!< GPIO DINOFF: DINOFF3 Position          */
#define GPIO_DINOFF_DINOFF3_Msk          (0x1ul << GPIO_DINOFF_DINOFF3_Pos)                /*!< GPIO DINOFF: DINOFF3 Mask              */

#define GPIO_DINOFF_DINOFF4_Pos          (20)                                              /*!< GPIO DINOFF: DINOFF4 Position          */
#define GPIO_DINOFF_DINOFF4_Msk          (0x1ul << GPIO_DINOFF_DINOFF4_Pos)                /*!< GPIO DINOFF: DINOFF4 Mask              */

#define GPIO_DINOFF_DINOFF5_Pos          (21)                                              /*!< GPIO DINOFF: DINOFF5 Position          */
#define GPIO_DINOFF_DINOFF5_Msk          (0x1ul << GPIO_DINOFF_DINOFF5_Pos)                /*!< GPIO DINOFF: DINOFF5 Mask              */

#define GPIO_DINOFF_DINOFF6_Pos          (22)                                              /*!< GPIO DINOFF: DINOFF6 Position          */
#define GPIO_DINOFF_DINOFF6_Msk          (0x1ul << GPIO_DINOFF_DINOFF6_Pos)                /*!< GPIO DINOFF: DINOFF6 Mask              */

#define GPIO_DINOFF_DINOFF7_Pos          (23)                                              /*!< GPIO DINOFF: DINOFF7 Position          */
#define GPIO_DINOFF_DINOFF7_Msk          (0x1ul << GPIO_DINOFF_DINOFF7_Pos)                /*!< GPIO DINOFF: DINOFF7 Mask              */

#define GPIO_DINOFF_DINOFF8_Pos          (24)                                              /*!< GPIO DINOFF: DINOFF8 Position          */
#define GPIO_DINOFF_DINOFF8_Msk          (0x1ul << GPIO_DINOFF_DINOFF8_Pos)                /*!< GPIO DINOFF: DINOFF8 Mask              */

#define GPIO_DINOFF_DINOFF9_Pos          (25)                                              /*!< GPIO DINOFF: DINOFF9 Position          */
#define GPIO_DINOFF_DINOFF9_Msk          (0x1ul << GPIO_DINOFF_DINOFF9_Pos)                /*!< GPIO DINOFF: DINOFF9 Mask              */

#define GPIO_DINOFF_DINOFF10_Pos         (26)                                              /*!< GPIO DINOFF: DINOFF10 Position         */
#define GPIO_DINOFF_DINOFF10_Msk         (0x1ul << GPIO_DINOFF_DINOFF10_Pos)               /*!< GPIO DINOFF: DINOFF10 Mask             */

#define GPIO_DINOFF_DINOFF11_Pos         (27)                                              /*!< GPIO DINOFF: DINOFF11 Position         */
#define GPIO_DINOFF_DINOFF11_Msk         (0x1ul << GPIO_DINOFF_DINOFF11_Pos)               /*!< GPIO DINOFF: DINOFF11 Mask             */

#define GPIO_DINOFF_DINOFF12_Pos         (28)                                              /*!< GPIO DINOFF: DINOFF12 Position         */
#define GPIO_DINOFF_DINOFF12_Msk         (0x1ul << GPIO_DINOFF_DINOFF12_Pos)               /*!< GPIO DINOFF: DINOFF12 Mask             */

#define GPIO_DINOFF_DINOFF13_Pos         (29)                                              /*!< GPIO DINOFF: DINOFF13 Position         */
#define GPIO_DINOFF_DINOFF13_Msk         (0x1ul << GPIO_DINOFF_DINOFF13_Pos)               /*!< GPIO DINOFF: DINOFF13 Mask             */

#define GPIO_DINOFF_DINOFF14_Pos         (30)                                              /*!< GPIO DINOFF: DINOFF14 Position         */
#define GPIO_DINOFF_DINOFF14_Msk         (0x1ul << GPIO_DINOFF_DINOFF14_Pos)               /*!< GPIO DINOFF: DINOFF14 Mask             */

#define GPIO_DINOFF_DINOFF15_Pos         (31)                                              /*!< GPIO DINOFF: DINOFF15 Position         */
#define GPIO_DINOFF_DINOFF15_Msk         (0x1ul << GPIO_DINOFF_DINOFF15_Pos)               /*!< GPIO DINOFF: DINOFF15 Mask             */

#define GPIO_DOUT_DOUT_Pos               (0)                                               /*!< GPIO DOUT: DOUT Position               */
#define GPIO_DOUT_DOUT_Msk               (0xfffful << GPIO_DOUT_DOUT_Pos)                  /*!< GPIO DOUT: DOUT Mask                   */

#define GPIO_DATMSK_DATMSK_Pos           (0)                                               /*!< GPIO DATMSK: DATMSK Position           */
#define GPIO_DATMSK_DATMSK_Msk           (0xfffful << GPIO_DATMSK_DATMSK_Pos)              /*!< GPIO DATMSK: DATMSK Mask               */

#define GPIO_PIN_PIN_Pos                 (0)                                               /*!< GPIO PIN: PIN Position                 */
#define GPIO_PIN_PIN_Msk                 (0xfffful << GPIO_PIN_PIN_Pos)                    /*!< GPIO PIN: PIN Mask                     */

#define GPIO_INTTYPE_TYPE_Pos            (0)                                               /*!< GPIO INTTYPE: TYPE Position            */
#define GPIO_INTTYPE_TYPE_Msk            (0xfffful << GPIO_INTTYPE_TYPE_Pos)               /*!< GPIO INTTYPE: TYPE Mask                */

#define GPIO_INTEN_FLIEN0_Pos            (0)                                               /*!< GPIO INTEN: FLIEN0 Position            */
#define GPIO_INTEN_FLIEN0_Msk            (0x1ul << GPIO_INTEN_FLIEN0_Pos)                  /*!< GPIO INTEN: FLIEN0 Mask                */

#define GPIO_INTEN_FLIEN1_Pos            (1)                                               /*!< GPIO INTEN: FLIEN1 Position            */
#define GPIO_INTEN_FLIEN1_Msk            (0x1ul << GPIO_INTEN_FLIEN1_Pos)                  /*!< GPIO INTEN: FLIEN1 Mask                */

#define GPIO_INTEN_FLIEN2_Pos            (2)                                               /*!< GPIO INTEN: FLIEN2 Position            */
#define GPIO_INTEN_FLIEN2_Msk            (0x1ul << GPIO_INTEN_FLIEN2_Pos)                  /*!< GPIO INTEN: FLIEN2 Mask                */

#define GPIO_INTEN_FLIEN3_Pos            (3)                                               /*!< GPIO INTEN: FLIEN3 Position            */
#define GPIO_INTEN_FLIEN3_Msk            (0x1ul << GPIO_INTEN_FLIEN3_Pos)                  /*!< GPIO INTEN: FLIEN3 Mask                */

#define GPIO_INTEN_FLIEN4_Pos            (4)                                               /*!< GPIO INTEN: FLIEN4 Position            */
#define GPIO_INTEN_FLIEN4_Msk            (0x1ul << GPIO_INTEN_FLIEN4_Pos)                  /*!< GPIO INTEN: FLIEN4 Mask                */

#define GPIO_INTEN_FLIEN5_Pos            (5)                                               /*!< GPIO INTEN: FLIEN5 Position            */
#define GPIO_INTEN_FLIEN5_Msk            (0x1ul << GPIO_INTEN_FLIEN5_Pos)                  /*!< GPIO INTEN: FLIEN5 Mask                */

#define GPIO_INTEN_FLIEN6_Pos            (6)                                               /*!< GPIO INTEN: FLIEN6 Position            */
#define GPIO_INTEN_FLIEN6_Msk            (0x1ul << GPIO_INTEN_FLIEN6_Pos)                  /*!< GPIO INTEN: FLIEN6 Mask                */

#define GPIO_INTEN_FLIEN7_Pos            (7)                                               /*!< GPIO INTEN: FLIEN7 Position            */
#define GPIO_INTEN_FLIEN7_Msk            (0x1ul << GPIO_INTEN_FLIEN7_Pos)                  /*!< GPIO INTEN: FLIEN7 Mask                */

#define GPIO_INTEN_FLIEN8_Pos            (8)                                               /*!< GPIO INTEN: FLIEN8 Position            */
#define GPIO_INTEN_FLIEN8_Msk            (0x1ul << GPIO_INTEN_FLIEN8_Pos)                  /*!< GPIO INTEN: FLIEN8 Mask                */

#define GPIO_INTEN_FLIEN9_Pos            (9)                                               /*!< GPIO INTEN: FLIEN9 Position            */
#define GPIO_INTEN_FLIEN9_Msk            (0x1ul << GPIO_INTEN_FLIEN9_Pos)                  /*!< GPIO INTEN: FLIEN9 Mask                */

#define GPIO_INTEN_FLIEN10_Pos           (10)                                              /*!< GPIO INTEN: FLIEN10 Position           */
#define GPIO_INTEN_FLIEN10_Msk           (0x1ul << GPIO_INTEN_FLIEN10_Pos)                 /*!< GPIO INTEN: FLIEN10 Mask               */

#define GPIO_INTEN_FLIEN11_Pos           (11)                                              /*!< GPIO INTEN: FLIEN11 Position           */
#define GPIO_INTEN_FLIEN11_Msk           (0x1ul << GPIO_INTEN_FLIEN11_Pos)                 /*!< GPIO INTEN: FLIEN11 Mask               */

#define GPIO_INTEN_FLIEN12_Pos           (12)                                              /*!< GPIO INTEN: FLIEN12 Position           */
#define GPIO_INTEN_FLIEN12_Msk           (0x1ul << GPIO_INTEN_FLIEN12_Pos)                 /*!< GPIO INTEN: FLIEN12 Mask               */

#define GPIO_INTEN_FLIEN13_Pos           (13)                                              /*!< GPIO INTEN: FLIEN13 Position           */
#define GPIO_INTEN_FLIEN13_Msk           (0x1ul << GPIO_INTEN_FLIEN13_Pos)                 /*!< GPIO INTEN: FLIEN13 Mask               */

#define GPIO_INTEN_FLIEN14_Pos           (14)                                              /*!< GPIO INTEN: FLIEN14 Position           */
#define GPIO_INTEN_FLIEN14_Msk           (0x1ul << GPIO_INTEN_FLIEN14_Pos)                 /*!< GPIO INTEN: FLIEN14 Mask               */

#define GPIO_INTEN_FLIEN15_Pos           (15)                                              /*!< GPIO INTEN: FLIEN15 Position           */
#define GPIO_INTEN_FLIEN15_Msk           (0x1ul << GPIO_INTEN_FLIEN15_Pos)                 /*!< GPIO INTEN: FLIEN15 Mask               */

#define GPIO_INTEN_RHIEN0_Pos            (16)                                              /*!< GPIO INTEN: RHIEN0 Position            */
#define GPIO_INTEN_RHIEN0_Msk            (0x1ul << GPIO_INTEN_RHIEN0_Pos)                  /*!< GPIO INTEN: RHIEN0 Mask                */

#define GPIO_INTEN_RHIEN1_Pos            (17)                                              /*!< GPIO INTEN: RHIEN1 Position            */
#define GPIO_INTEN_RHIEN1_Msk            (0x1ul << GPIO_INTEN_RHIEN1_Pos)                  /*!< GPIO INTEN: RHIEN1 Mask                */

#define GPIO_INTEN_RHIEN2_Pos            (18)                                              /*!< GPIO INTEN: RHIEN2 Position            */
#define GPIO_INTEN_RHIEN2_Msk            (0x1ul << GPIO_INTEN_RHIEN2_Pos)                  /*!< GPIO INTEN: RHIEN2 Mask                */

#define GPIO_INTEN_RHIEN3_Pos            (19)                                              /*!< GPIO INTEN: RHIEN3 Position            */
#define GPIO_INTEN_RHIEN3_Msk            (0x1ul << GPIO_INTEN_RHIEN3_Pos)                  /*!< GPIO INTEN: RHIEN3 Mask                */

#define GPIO_INTEN_RHIEN4_Pos            (20)                                              /*!< GPIO INTEN: RHIEN4 Position            */
#define GPIO_INTEN_RHIEN4_Msk            (0x1ul << GPIO_INTEN_RHIEN4_Pos)                  /*!< GPIO INTEN: RHIEN4 Mask                */

#define GPIO_INTEN_RHIEN5_Pos            (21)                                              /*!< GPIO INTEN: RHIEN5 Position            */
#define GPIO_INTEN_RHIEN5_Msk            (0x1ul << GPIO_INTEN_RHIEN5_Pos)                  /*!< GPIO INTEN: RHIEN5 Mask                */

#define GPIO_INTEN_RHIEN6_Pos            (22)                                              /*!< GPIO INTEN: RHIEN6 Position            */
#define GPIO_INTEN_RHIEN6_Msk            (0x1ul << GPIO_INTEN_RHIEN6_Pos)                  /*!< GPIO INTEN: RHIEN6 Mask                */

#define GPIO_INTEN_RHIEN7_Pos            (23)                                              /*!< GPIO INTEN: RHIEN7 Position            */
#define GPIO_INTEN_RHIEN7_Msk            (0x1ul << GPIO_INTEN_RHIEN7_Pos)                  /*!< GPIO INTEN: RHIEN7 Mask                */

#define GPIO_INTEN_RHIEN8_Pos            (24)                                              /*!< GPIO INTEN: RHIEN8 Position            */
#define GPIO_INTEN_RHIEN8_Msk            (0x1ul << GPIO_INTEN_RHIEN8_Pos)                  /*!< GPIO INTEN: RHIEN8 Mask                */

#define GPIO_INTEN_RHIEN9_Pos            (25)                                              /*!< GPIO INTEN: RHIEN9 Position            */
#define GPIO_INTEN_RHIEN9_Msk            (0x1ul << GPIO_INTEN_RHIEN9_Pos)                  /*!< GPIO INTEN: RHIEN9 Mask                */

#define GPIO_INTEN_RHIEN10_Pos           (26)                                              /*!< GPIO INTEN: RHIEN10 Position           */
#define GPIO_INTEN_RHIEN10_Msk           (0x1ul << GPIO_INTEN_RHIEN10_Pos)                 /*!< GPIO INTEN: RHIEN10 Mask               */

#define GPIO_INTEN_RHIEN11_Pos           (27)                                              /*!< GPIO INTEN: RHIEN11 Position           */
#define GPIO_INTEN_RHIEN11_Msk           (0x1ul << GPIO_INTEN_RHIEN11_Pos)                 /*!< GPIO INTEN: RHIEN11 Mask               */

#define GPIO_INTEN_RHIEN12_Pos           (28)                                              /*!< GPIO INTEN: RHIEN12 Position           */
#define GPIO_INTEN_RHIEN12_Msk           (0x1ul << GPIO_INTEN_RHIEN12_Pos)                 /*!< GPIO INTEN: RHIEN12 Mask               */

#define GPIO_INTEN_RHIEN13_Pos           (29)                                              /*!< GPIO INTEN: RHIEN13 Position           */
#define GPIO_INTEN_RHIEN13_Msk           (0x1ul << GPIO_INTEN_RHIEN13_Pos)                 /*!< GPIO INTEN: RHIEN13 Mask               */

#define GPIO_INTEN_RHIEN14_Pos           (30)                                              /*!< GPIO INTEN: RHIEN14 Position           */
#define GPIO_INTEN_RHIEN14_Msk           (0x1ul << GPIO_INTEN_RHIEN14_Pos)                 /*!< GPIO INTEN: RHIEN14 Mask               */

#define GPIO_INTEN_RHIEN15_Pos           (31)                                              /*!< GPIO INTEN: RHIEN15 Position           */
#define GPIO_INTEN_RHIEN15_Msk           (0x1ul << GPIO_INTEN_RHIEN15_Pos)                 /*!< GPIO INTEN: RHIEN15 Mask               */

#define GPIO_INTSRC_INTSRC_Pos           (0)                                               /*!< GPIO INTSRC: INTSRC Position           */
#define GPIO_INTSRC_INTSRC_Msk           (0xfffful << GPIO_INTSRC_INTSRC_Pos)              /*!< GPIO INTSRC: INTSRC Mask               */

/**@}*/ /* GPIO_CONST */
/**@}*/ /* end of GPIO register group */

/*---------------------- Pulse Width Modulation Controller -------------------------*/
/**
    @addtogroup PWM Pulse Width Modulation Controller(PWM)
    Memory Mapped Structure for PWM Controller
@{ */
 
typedef struct
{


    /**
     * CLKPSC
     * ===================================================================================================
     * Offset: 0x00  PWM Prescaler Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:7]   |CLKPSC    |Clock Prescaler For PWM Timer
     * |        |          |Clock input is divided by (CLKPSC + 1)
     * |        |          |If CLKPSC = 0, then the prescaler output clock will be stopped.
     * |        |          |This implies PWM counter will also be stopped.
     * |[16:23] |DZI0      |Dead Zone Interval Register 0
     * |        |          |These 8 bits determine dead zone length.
     * |        |          |The unit time of dead zone length is that from clock selector.
     * |[24:31] |DZI1      |Dead Zone Interval Register 1
     * |        |          |These 8 bits determine dead zone length.
     * |        |          |The unit time of dead zone length is that from clock selector.
 */
    __IO uint32_t CLKPSC;                

    /**
     * CLKDIV
     * ===================================================================================================
     * Offset: 0x04  PWM Clock Select Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:2]   |CLKDIV    |PWM Timer Clock Source Selection
     * |        |          |Value : Input clock divided by
     * |        |          |000 : 2
     * |        |          |001 : 4
     * |        |          |010 : 8
     * |        |          |011 : 16
     * |        |          |1xx : 1
 */
    __IO uint32_t CLKDIV;                

    /**
     * CTL
     * ===================================================================================================
     * Offset: 0x08  PWM Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |CNTEN     |PWM-Timer Enable
     * |        |          |0 = Stop PWM-Timer Running.
     * |        |          |1 = Enable PWM-Timer.
     * |[2]     |PINV      |PWM-Timer Output Inverter ON/OFF
     * |        |          |0 = Inverter OFF.
     * |        |          |1 = Inverter ON.
     * |[3]     |CNTMODE   |PWM-Timer Auto-Reload/One-Shot Mode
     * |        |          |0 = One-Shot Mode.
     * |        |          |1 = Auto-reload Mode.
     * |[4]     |DTEN0     |Dead-Zone 0 Generator Enable/Disable
     * |        |          |0 = Disable.
     * |        |          |1 = Enable.
     * |[5]     |DTEN1     |Dead-Zone 1 Generator Enable/Disable
     * |        |          |0 = Disable.
     * |        |          |1 = Enable.
 */
    __IO uint32_t CTL;                   

    /**
     * PERIOD
     * ===================================================================================================
     * Offset: 0x0C  PWM Period Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |PERIOD    |PWM Counter/Timer Reload Value
     * |        |          |PERIOD determines the PWM period.
     * |        |          |Note: One PWM cycle width = (PERIOD + 1).
 */
    __IO uint32_t PERIOD;                

    /**
     * CMPDAT0
     * ===================================================================================================
     * Offset: 0x10  PWM Comparator Register 0
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |CMP       |PWM Comparator Register
     * |        |          |CMP determines the PWM duty cycle.
     * |        |          |Assumption: PWM output initial is high
     * |        |          |CMP > = PERIOD: PWM output is always high.
     * |        |          |CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
     * |        |          |CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
     * |        |          |Note1: Unit = one PWM clock cycle.
     * |        |          |Note2: Any write to CMP will take effect in next PWM cycle.
 */
    __IO uint32_t CMPDAT0;               

    /**
     * CNT
     * ===================================================================================================
     * Offset: 0x14  PWM Counter Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |CNT       |PWM Counter Register
     * |        |          |Reports the current value of the 16-bit down counter.
 */
    __I  uint32_t CNT;                   
         uint32_t RESERVE0[1];


    /**
     * CMPDAT1
     * ===================================================================================================
     * Offset: 0x1C  PWM Comparator Register 1
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |CMP       |PWM Comparator Register
     * |        |          |CMP determines the PWM duty cycle.
     * |        |          |Assumption: PWM output initial is high
     * |        |          |CMP > = PERIOD: PWM output is always high.
     * |        |          |CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
     * |        |          |CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
     * |        |          |Note1: Unit = one PWM clock cycle.
     * |        |          |Note2: Any write to CMP will take effect in next PWM cycle.
 */
    __IO uint32_t CMPDAT1;               
         uint32_t RESERVE1[2];


    /**
     * CMPDAT2
     * ===================================================================================================
     * Offset: 0x28  PWM Comparator Register 2
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |CMP       |PWM Comparator Register
     * |        |          |CMP determines the PWM duty cycle.
     * |        |          |Assumption: PWM output initial is high
     * |        |          |CMP > = PERIOD: PWM output is always high.
     * |        |          |CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
     * |        |          |CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
     * |        |          |Note1: Unit = one PWM clock cycle.
     * |        |          |Note2: Any write to CMP will take effect in next PWM cycle.
 */
    __IO uint32_t CMPDAT2;               
         uint32_t RESERVE2[2];


    /**
     * CMPDAT3
     * ===================================================================================================
     * Offset: 0x34  PWM Comparator Register 3
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |CMP       |PWM Comparator Register
     * |        |          |CMP determines the PWM duty cycle.
     * |        |          |Assumption: PWM output initial is high
     * |        |          |CMP > = PERIOD: PWM output is always high.
     * |        |          |CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
     * |        |          |CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
     * |        |          |Note1: Unit = one PWM clock cycle.
     * |        |          |Note2: Any write to CMP will take effect in next PWM cycle.
 */
    __IO uint32_t CMPDAT3;               
         uint32_t RESERVE3[2];


    /**
     * INTEN
     * ===================================================================================================
     * Offset: 0x40  PWM Interrupt Enable Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |PIEN      |PWM Timer Interrupt Enable
     * |        |          |0 = Disable.
     * |        |          |1 = Enable.
 */
    __IO uint32_t INTEN;                 

    /**
     * INTSTS
     * ===================================================================================================
     * Offset: 0x44  PWM Interrupt Flag Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |PIF       |PWM Timer Interrupt Flag
     * |        |          |Flag is set by hardware when PWM down counter reaches zero, software can clear this bit by writing '1' to it.
 */
    __IO uint32_t INTSTS;                
         uint32_t RESERVE4[2];


    /**
     * CAPCTL
     * ===================================================================================================
     * Offset: 0x50  Capture Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |CAPINV    |Inverter ON/OFF
     * |        |          |0 = Inverter OFF.
     * |        |          |1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
     * |[1]     |CRLIEN    |Rising Latch Interrupt Enable ON/OFF
     * |        |          |0 = Disable rising latch interrupt.
     * |        |          |1 = Enable rising latch interrupt.
     * |        |          |When enabled, capture block generates an interrupt on rising edge of input.
     * |[2]     |CFLIEN    |Falling Latch Interrupt Enable ON/OFF
     * |        |          |0 = Disable falling latch interrupt.
     * |        |          |1 = Enable falling latch interrupt.
     * |        |          |When enabled, capture block generates an interrupt on falling edge of input.
     * |[3]     |CAPEN     |Capture Channel Input Transition Enable/Disable
     * |        |          |0 = Disable capture function.
     * |        |          |1 = Enable capture function.
     * |        |          |When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
     * |        |          |When disabled, Capture function is inactive as is interrupt.
     * |[4]     |CAPIF     |Capture Interrupt Indication Flag
     * |        |          |When capture input has a falling/rising transition and falling/rising latch interrupt is enabled (CFLIEN = 1/CRLIEN = 1), CAPIF0 is set 1 by hardware.
     * |        |          |Software can clear this bit by writing a one to it.
     * |        |          |Note:
     * |        |          |If this bit is "1", PWM counter will not be reloaded when next capture interrupt occurs.
     * |[6]     |CRLIF     |PWM_RCAPDAT Latched Indicator Bit
     * |        |          |When input channel has a rising transition, PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
     * |[7]     |CFLIF     |PWM_FCAPDAT Latched Indicator Bit
     * |        |          |When input channel has a falling transition, PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it
 */
    __IO uint32_t CAPCTL;                
         uint32_t RESERVE5[1];


    /**
     * RCAPDAT
     * ===================================================================================================
     * Offset: 0x58  Capture Rising Latch Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |RCAPDAT   |Capture Rising Latch Register
     * |        |          |In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.
 */
    __I  uint32_t RCAPDAT;               

    /**
     * FCAPDAT
     * ===================================================================================================
     * Offset: 0x5C  Capture Falling Latch Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |FCAPDAT   |Capture Falling Latch Register
     * |        |          |In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.
 */
    __I  uint32_t FCAPDAT;               
         uint32_t RESERVE6[7];


    /**
     * PCEN
     * ===================================================================================================
     * Offset: 0x7C  PWM Output and Capture Input Enable Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |POEN0     |PWM0 Output Enable Register
     * |        |          |0 = Disable PWM0 output to pin.
     * |        |          |1 = Enable PWM0 output to pin.
     * |        |          |Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 5-8)
     * |[1]     |POEN1     |PWM1 Output Enable Register
     * |        |          |0 = Disable PWM1 output to pin.
     * |        |          |1 = Enable PWM1 output to pin.
     * |        |          |Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 5-8)
     * |[2]     |POEN2     |PWM2 Output Enable Register
     * |        |          |0 = Disable PWM2 output to pin.
     * |        |          |1 = Enable PWM2 output to pin.
     * |        |          |Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 5-8)
     * |[3]     |POEN3     |PWM3 Output Enable Register
     * |        |          |0 = Disable PWM3 output to pin.
     * |        |          |1 = Enable PWM3 output to pin.
     * |        |          |Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPB_MFP Table 5-8)
     * |[8]     |CAPINEN   |Capture Input Enable Register
     * |        |          |0 = OFF (PB.12 pin input disconnected from Capture block).
     * |        |          |1 = ON (PB.12 pin, if in PWM alternative function, will be configured as an input and fed to capture function).
 */
    __IO uint32_t PCEN;                  

} PWM_T;

/**
    @addtogroup PWM_CONST PWM Bit Field Definition
    Constant Definitions for PWM Controller
@{ */

#define PWM_CLKPSC_CLKPSC_Pos            (0)                                               /*!< PWM CLKPSC: CLKPSC Position            */
#define PWM_CLKPSC_CLKPSC_Msk            (0xfful << PWM_CLKPSC_CLKPSC_Pos)                 /*!< PWM CLKPSC: CLKPSC Mask                */

#define PWM_CLKPSC_DZI0_Pos              (16)                                              /*!< PWM CLKPSC: DZI0 Position              */
#define PWM_CLKPSC_DZI0_Msk              (0xfful << PWM_CLKPSC_DZI0_Pos)                   /*!< PWM CLKPSC: DZI0 Mask                  */

#define PWM_CLKPSC_DZI1_Pos              (24)                                              /*!< PWM CLKPSC: DZI1 Position              */
#define PWM_CLKPSC_DZI1_Msk              (0xfful << PWM_CLKPSC_DZI1_Pos)                   /*!< PWM CLKPSC: DZI1 Mask                  */

#define PWM_CLKDIV_CLKDIV_Pos           (0)                                                /*!< PWM CLKDIV: CLKDIV Position           */
#define PWM_CLKDIV_CLKDIV_Msk           (0x7ul << PWM_CLKDIV_CLKDIV_Pos)                   /*!< PWM CLKDIV: CLKDIV Mask               */

#define PWM_CTL_CNTEN_Pos                (0)                                               /*!< PWM CTL: CNTEN Position                */
#define PWM_CTL_CNTEN_Msk                (0x1ul << PWM_CTL_CNTEN_Pos)                      /*!< PWM CTL: CNTEN Mask                    */

#define PWM_CTL_PINV_Pos                 (2)                                               /*!< PWM CTL: PINV Position                 */
#define PWM_CTL_PINV_Msk                 (0x1ul << PWM_CTL_PINV_Pos)                       /*!< PWM CTL: PINV Mask                     */

#define PWM_CTL_CNTMODE_Pos              (3)                                               /*!< PWM CTL: CNTMODE Position              */
#define PWM_CTL_CNTMODE_Msk              (0x1ul << PWM_CTL_CNTMODE_Pos)                    /*!< PWM CTL: CNTMODE Mask                  */

#define PWM_CTL_DTEN0_Pos                (4)                                               /*!< PWM CTL: DTEN0 Position                */
#define PWM_CTL_DTEN0_Msk                (0x1ul << PWM_CTL_DTEN0_Pos)                      /*!< PWM CTL: DTEN0 Mask                    */

#define PWM_CTL_DTEN1_Pos                (5)                                               /*!< PWM CTL: DTEN1 Position                */
#define PWM_CTL_DTEN1_Msk                (0x1ul << PWM_CTL_DTEN1_Pos)                      /*!< PWM CTL: DTEN1 Mask                    */

#define PWM_PERIOD_PERIOD_Pos            (0)                                               /*!< PWM PERIOD: PERIOD Position            */
#define PWM_PERIOD_PERIOD_Msk            (0xfffful << PWM_PERIOD_PERIOD_Pos)               /*!< PWM PERIOD: PERIOD Mask                */

#define PWM_CMPDAT0_CMP_Pos              (0)                                               /*!< PWM CMPDAT0: CMP Position              */
#define PWM_CMPDAT0_CMP_Msk              (0xfffful << PWM_CMPDAT0_CMP_Pos)                 /*!< PWM CMPDAT0: CMP Mask                  */

#define PWM_CNT_CNT_Pos                  (0)                                               /*!< PWM CNT: CNT Position                  */
#define PWM_CNT_CNT_Msk                  (0xfffful << PWM_CNT_CNT_Pos)                     /*!< PWM CNT: CNT Mask                      */

#define PWM_CMPDAT1_CMP_Pos              (0)                                               /*!< PWM CMPDAT1: CMP Position              */
#define PWM_CMPDAT1_CMP_Msk              (0xfffful << PWM_CMPDAT1_CMP_Pos)                 /*!< PWM CMPDAT1: CMP Mask                  */

#define PWM_CMPDAT2_CMP_Pos              (0)                                               /*!< PWM CMPDAT2: CMP Position              */
#define PWM_CMPDAT2_CMP_Msk              (0xfffful << PWM_CMPDAT2_CMP_Pos)                 /*!< PWM CMPDAT2: CMP Mask                  */

#define PWM_CMPDAT3_CMP_Pos              (0)                                               /*!< PWM CMPDAT3: CMP Position              */
#define PWM_CMPDAT3_CMP_Msk              (0xfffful << PWM_CMPDAT3_CMP_Pos)                 /*!< PWM CMPDAT3: CMP Mask                  */

#define PWM_INTEN_PIEN_Pos               (0)                                               /*!< PWM INTEN: PIEN Position               */
#define PWM_INTEN_PIEN_Msk               (0x1ul << PWM_INTEN_PIEN_Pos)                     /*!< PWM INTEN: PIEN Mask                   */

#define PWM_INTSTS_PIF_Pos               (0)                                               /*!< PWM INTSTS: PIF Position               */
#define PWM_INTSTS_PIF_Msk               (0x1ul << PWM_INTSTS_PIF_Pos)                     /*!< PWM INTSTS: PIF Mask                   */

#define PWM_CAPCTL_CAPINV_Pos            (0)                                               /*!< PWM CAPCTL: CAPINV Position            */
#define PWM_CAPCTL_CAPINV_Msk            (0x1ul << PWM_CAPCTL_CAPINV_Pos)                  /*!< PWM CAPCTL: CAPINV Mask                */

#define PWM_CAPCTL_CRLIEN_Pos            (1)                                               /*!< PWM CAPCTL: CRLIEN Position            */
#define PWM_CAPCTL_CRLIEN_Msk            (0x1ul << PWM_CAPCTL_CRLIEN_Pos)                  /*!< PWM CAPCTL: CRLIEN Mask                */

#define PWM_CAPCTL_CFLIEN_Pos            (2)                                               /*!< PWM CAPCTL: CFLIEN Position            */
#define PWM_CAPCTL_CFLIEN_Msk            (0x1ul << PWM_CAPCTL_CFLIEN_Pos)                  /*!< PWM CAPCTL: CFLIEN Mask                */

#define PWM_CAPCTL_CAPEN_Pos             (3)                                               /*!< PWM CAPCTL: CAPEN Position             */
#define PWM_CAPCTL_CAPEN_Msk             (0x1ul << PWM_CAPCTL_CAPEN_Pos)                   /*!< PWM CAPCTL: CAPEN Mask                 */

#define PWM_CAPCTL_CAPIF_Pos             (4)                                               /*!< PWM CAPCTL: CAPIF Position             */
#define PWM_CAPCTL_CAPIF_Msk             (0x1ul << PWM_CAPCTL_CAPIF_Pos)                   /*!< PWM CAPCTL: CAPIF Mask                 */

#define PWM_CAPCTL_CRLIF_Pos             (6)                                               /*!< PWM CAPCTL: CRLIF Position             */
#define PWM_CAPCTL_CRLIF_Msk             (0x1ul << PWM_CAPCTL_CRLIF_Pos)                   /*!< PWM CAPCTL: CRLIF Mask                 */

#define PWM_CAPCTL_CFLIF_Pos             (7)                                               /*!< PWM CAPCTL: CFLIF Position             */
#define PWM_CAPCTL_CFLIF_Msk             (0x1ul << PWM_CAPCTL_CFLIF_Pos)                   /*!< PWM CAPCTL: CFLIF Mask                 */

#define PWM_RCAPDAT_RCAPDAT_Pos          (0)                                               /*!< PWM RCAPDAT: RCAPDAT Position          */
#define PWM_RCAPDAT_RCAPDAT_Msk          (0xfffful << PWM_RCAPDAT_RCAPDAT_Pos)             /*!< PWM RCAPDAT: RCAPDAT Mask              */

#define PWM_FCAPDAT_FCAPDAT_Pos          (0)                                               /*!< PWM FCAPDAT: FCAPDAT Position          */
#define PWM_FCAPDAT_FCAPDAT_Msk          (0xfffful << PWM_FCAPDAT_FCAPDAT_Pos)             /*!< PWM FCAPDAT: FCAPDAT Mask              */

#define PWM_PCEN_POEN0_Pos               (0)                                               /*!< PWM PCEN: POEN0 Position               */
#define PWM_PCEN_POEN0_Msk               (0x1ul << PWM_PCEN_POEN0_Pos)                     /*!< PWM PCEN: POEN0 Mask                   */

#define PWM_PCEN_POEN1_Pos               (1)                                               /*!< PWM PCEN: POEN1 Position               */
#define PWM_PCEN_POEN1_Msk               (0x1ul << PWM_PCEN_POEN1_Pos)                     /*!< PWM PCEN: POEN1 Mask                   */

#define PWM_PCEN_POEN2_Pos               (2)                                               /*!< PWM PCEN: POEN2 Position               */
#define PWM_PCEN_POEN2_Msk               (0x1ul << PWM_PCEN_POEN2_Pos)                     /*!< PWM PCEN: POEN2 Mask                   */

#define PWM_PCEN_POEN3_Pos               (3)                                               /*!< PWM PCEN: POEN3 Position               */
#define PWM_PCEN_POEN3_Msk               (0x1ul << PWM_PCEN_POEN3_Pos)                     /*!< PWM PCEN: POEN3 Mask                   */

#define PWM_PCEN_CAPINEN_Pos             (8)                                               /*!< PWM PCEN: CAPINEN Position             */
#define PWM_PCEN_CAPINEN_Msk             (0x1ul << PWM_PCEN_CAPINEN_Pos)                   /*!< PWM PCEN: CAPINEN Mask                 */

/**@}*/ /* PWM_CONST */
/**@}*/ /* end of PWM register group */


/*---------------------- Real Time Clock Controller -------------------------*/
/**
    @addtogroup RTC Real Time Clock Controller(RTC)
    Memory Mapped Structure for RTC Controller
@{ */
 
typedef struct
{


    /**
     * CTL
     * ===================================================================================================
     * Offset: 0x00  RTC Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |RTIF      |RTC Interrupt Flag
     * |        |          |If the RTC interrupt is enabled, then the hardware will set this bit to indicate that the RTC interrupt has occurred.
     * |        |          |If the RTC interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
     * |        |          |0 = RTC interrupt does not occur.
     * |        |          |1 = RTC interrupt occurs.
     * |        |          |Note: This bit is cleared by writing 1 to this bit.
     * |[1]     |RTIE      |RTC Interrupt Enable
     * |        |          |0 = Disable the RTC interrupt.
     * |        |          |1 = Enable the RTC interrupt.
     * |[2]     |RTCE      |RTC Enable
     * |        |          |0 = Disable RTC function.
     * |        |          |1 = Enable RTC function.
     * |[3:4]   |RTIS      |RTC Timer Interval Select
     * |        |          |These two bits select the timeout interval for the RTC.
     * |        |          |00 = Time-out frequency is 0.25Hz,.
     * |        |          |01 = Time-out frequency is 2Hz,.
     * |        |          |10 = Time-out frequency is 8Hz,.
     * |        |          |11 = Time-out frequency is 32Hz.
 */
    __IO uint32_t CTL;                   

} RTC_T;

/**
    @addtogroup RTC_CONST RTC Bit Field Definition
    Constant Definitions for RTC Controller
@{ */

#define RTC_CTL_RTIF_Pos                 (0)                                               /*!< RTC CTL: RTIF Position                 */
#define RTC_CTL_RTIF_Msk                 (0x1ul << RTC_CTL_RTIF_Pos)                       /*!< RTC CTL: RTIF Mask                     */

#define RTC_CTL_RTIE_Pos                 (1)                                               /*!< RTC CTL: RTIE Position                 */
#define RTC_CTL_RTIE_Msk                 (0x1ul << RTC_CTL_RTIE_Pos)                       /*!< RTC CTL: RTIE Mask                     */

#define RTC_CTL_RTCE_Pos                 (2)                                               /*!< RTC CTL: RTCE Position                 */
#define RTC_CTL_RTCE_Msk                 (0x1ul << RTC_CTL_RTCE_Pos)                       /*!< RTC CTL: RTCE Mask                     */

#define RTC_CTL_RTIS_Pos                 (3)                                               /*!< RTC CTL: RTIS Position                 */
#define RTC_CTL_RTIS_Msk                 (0x3ul << RTC_CTL_RTIS_Pos)                       /*!< RTC CTL: RTIS Mask                     */

/**@}*/ /* RTC_CONST */
/**@}*/ /* end of RTC register group */


/*---------------------- Serial Peripheral Interface Controller -------------------------*/
/**
    @addtogroup SPI Serial Peripheral Interface Controller(SPI)
    Memory Mapped Structure for SPI Controller
@{ */
 
typedef struct
{


    /**
     * CTL
     * ===================================================================================================
     * Offset: 0x00  Control and Status Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |GO_BUSY   |Go And Busy Status
     * |        |          |0 = Writing 0 to this bit has no effect.
     * |        |          |1 = Writing 1 to this bit starts the transfer.
     * |        |          |This bit remains "1" during the transfer and is automatically cleared after the transfer is finished.
     * |        |          |NOTE: All registers should be set readily before writing 1 to the GO_BUSY bit.
     * |        |          |When a transfer is in progress, writing to any register of the SPI core has no effect.
     * |[1]     |RX_NEG    |Receive On Negative Edge
     * |        |          |0 = The input on SPI_MISOn is latched on the rising edge of SPI_SCLKn.
     * |        |          |1 = The input on SPI_MISOn is latched on the falling edge of SPI_SCLKn. 
     * |[2]     |TX_NEG    |Transmit On Negative Edge
     * |        |          |0 = The output on SPI_MOSIn is changed on the rising edge of SPI_SCLKn.
     * |        |          |1 = The output on SPI_MOSIn is changed on the falling edge of SPI_SCLKn. 
     * |[3:7]   |TX_BIT_LEN|Transmit Bit Length
     * |        |          |This field specifies how many bits are transmitted in one transmit/receive.
     * |        |          |Up to 32 bits can be transmitted.
     * |        |          |TX_BIT_LEN = 0x01 ... 1 bit
     * |        |          |TX_BIT_LEN = 0x02 ... 2 bits
     * |        |          |......
     * |        |          |TX_BIT_LEN = 0x1F ... 31 bits
     * |        |          |TX_BIT_LEN = 0x00 ... 32 bits.
     * |[8:9]   |TX_NUM    |Transmit/Receive Numbers
     * |        |          |This field specifies how many transmit/receive numbers should be executed in one transfer.
     * |        |          |00 = Only one transmit/receive will be executed in one transfer.
     * |        |          |01 = Two successive transmit/receive will be executed in one transfer.
     * |        |          |1x = Reserved.
     * |[10]    |LSB       |Send LSB First
     * |        |          |0 = The MSB is transmitted/received first (which bit in SPI_TXn/SPI_RXn is MSB is dependent on TX_BIT_LEN).
     * |        |          |1 = The LSB (SPI_TXn[0]) is sent first to SPI_MOSIn, and the first bit received from SPI_MISOn will be put in the LSB (SPI_RXn[0]).
     * |[11]    |CLKP      |Clock Polarity
     * |        |          |0 = SPI_SCLKn idle low.
     * |        |          |1 = SPI_SCLKn idle high.
     * |[12:15] |SLEEP     |Suspend Interval (Master Mode Only)
     * |        |          |These four bits provide the configuration of suspend interval between two successive transmit/receive in a transfer.
     * |        |          |The default value is 0.
     * |        |          |When TX_NUM=00, setting this field has no effect on transfer.
     * |        |          |The desired interval is obtained according to the following equation (from the last falling edge of SPI_SCLKn pin to the next rising edge of SPI_SCLKn pin):.
     * |        |          |(SLEEP+2)* SPI_SCLKn.
     * |        |          |Note: SLEEP cannot be "0" for SPI0.
     * |[16]    |SPIIF     |Interrupt Flag
     * |        |          |0 = It indicates that the transfer does not finish yet.
     * |        |          |1 = It indicates that the transfer is done. The interrupt flag is set if SPI interrupt was enabled.
     * |        |          |NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
     * |[17]    |SPIIE     |Interrupt Enable
     * |        |          |0 = Disable SPI interrupt,.
     * |        |          |1 = Enable SPI interrupt.
     * |[18]    |SLAVE     |Master/Slave Mode Select
     * |        |          |0 = Master mode.
     * |        |          |1 = Slave mode.
     * |        |          |This bit exists in SPI1 only. SPI0 only supports master mode and it does not have this bit. 
     * |[20]    |BYTE_ENDIAN|BYTE ENDIAN
     * |        |          |0 = Disable the BYTE ENDIAN.
     * |        |          |1 = Enable the BYTE ENDIAN. Only the 16, 24, and 32 bits which are defined in TX_BIT_LEN are supported.
     * |        |          |When the transition is set as MSB first and BYTE_ENDIAN=1, the data stored in the SPI_TXn buffer will be arranged in the order as [BYTE0, BYTE1, BYTE2, BYTE3] in TX_BIT_LEN=32-bit mode, and the sequence of transmitted data will be BYTE0, BYTE1, BYTE2, and BYTE3.
     * |        |          |If the TX_BIT_LEN is set as 24-bit mode, the data in SPI_TXn buffer will be arranged as [unknown_byte, BYTE0, BYTE1, BYTE2] and the BYTE0, BYTE1, and BYTE2 will be transmitted step by step in MSB first.
     * |        |          |The rule of 16-bit mode is the same as above.
 */
    __IO uint32_t CTL;                   

    /**
     * CLKDIV
     * ===================================================================================================
     * Offset: 0x04  Clock Divider Register (Master Only)
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |DIVIDER   |Clock Divider Register (Master Mode Only)
     * |        |          |SPI0:
     * |        |          |SPI0 clock pin SPI_SCLK0 output clock frequency is SPI0_CIN/(DIVIDER+1).
     * |        |          |DIVIDER can be from 0 to 65535.
     * |        |          |SPI1:
     * |        |          |SPI1 clock pin SPI_SCLK1 output clock frequency is SPI1_CIN/2*(DIVIDER+1).
     * |        |          |Suggest DIVIDER should be at least 1 in master mode.
     * |        |          |In slave mode, the period of SPI_SCLK1 clock input shall be equal or over 5 times HCLK at least.
 */
    __IO uint32_t CLKDIV;                

    /**
     * SSCTL
     * ===================================================================================================
     * Offset: 0x08  Slave Select Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:1]   |SSPC      |Slave Select Pin Control (Master Mode Only)
     * |        |          |If ASS bit is 0, SPI_SSBx0 and SPI_SSBx1 output are determined by SSPC[0] and SSPC[1] respectively.
     * |        |          |Writing 1 to any bit location of this field forces the proper SPI_SSBx0/SPI_SSBx1 pin to an active state and writing 0 forces the pin back to inactive state.
     * |        |          |If ASS bit is 1, writing 1 to any bit location of this field will select appropriate SPI_SSBx0/SPI_SSBx1 pin to be automatically driven to active state for the duration of the transmit/receive, and to be driven to inactive state for the rest of the time.
     * |        |          |Writing 0 to any bit location of this field will select appropriate SPI_SSBx0/SPI_SSBx1 pin to be driven to inactive state.
     * |[2]     |SS_LVL    |Slave Select Active Level
     * |        |          |It defines the active level of device/slave select signal.
     * |        |          |0 = The SPI_SSBx0/SPI_SSBx1 slave select signal is active Low.
     * |        |          |1 = The SPI_SSBx0/SPI_SSBx1 slave select signal is active High.
     * |[3]     |ASS       |Automatic Slave Select (Master Mode Only)
     * |        |          |0 = Slave select signal (SPI_SSBx0/SPI_SSBx1) is asserted and de-asserted by setting and clearing related bit SSPC.
     * |        |          |1 = Slave select signal (SPI_SSBx0/SPI_SSBx1) is generated automatically.
     * |        |          |It means that slave select signal, which is set in bits SSPC, is asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after the transfer is finished.
     * |[4]     |SS_LTRIG  |Slave Select Level Trigger (Slave Mode Only)
     * |        |          |0 = The input slave select signal is edge-trigger. This is the default value.
     * |        |          |1 = The slave select signal will be level-trigger.
     * |        |          |It depends on SS_LVL to decide the signal is active low or active high.
     * |        |          |Note 1: This bit exists in SPI1 only. SPI0 only supports master mode and it does not have this bit.
     * |[5]     |LTRIG_FLAG|Level Trigger Flag (Slave Mode Only)
     * |        |          |When the SS_LTRIG
     * |        |          |bit is set in slave mode, this bit can be read to indicate the received bit number meets the requirement or not.
     * |        |          |0 = One of the received number and the received bit length doesn't meet the requirement in one transfer.
     * |        |          |1 = The received number and received bits meet the requirement which is defined in TX_NUM
     * |        |          |and TX_BIT_LEN among one transfer.
     * |        |          |Note 1: This bit is READ only.
     * |        |          |Note 2: This bit exists in SPI1 only. SPI0 only supports master mode and it does not have this bit.
 */
    __IO uint32_t SSCTL;                 
         uint32_t RESERVE0[1];


    /**
     * RX0
     * ===================================================================================================
     * Offset: 0x10  Data Receive Register 0
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:31]  |RX        |Data Receive Register
     * |        |          |The Data Receive Registers hold the value of received data of the last executed transfer.
     * |        |          |Valid bits depend on the transmit bit length field in the SPI_CTL register.
     * |        |          |For example, if TX_BIT_LEN=0x08 and TX_NUM=0x0, bits SPI_RX0[7:0] hold the received data.
     * |        |          |NOTE: The Data Receive Registers are read only registers.
     * |        |          |A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops.
 */
    __I  uint32_t RX0;                   

    /**
     * RX1
     * ===================================================================================================
     * Offset: 0x14  Data Receive Register 1
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:31]  |RX        |Data Receive Register
     * |        |          |The Data Receive Registers hold the value of received data of the last executed transfer.
     * |        |          |Valid bits depend on the transmit bit length field in the SPI_CTL register.
     * |        |          |For example, if TX_BIT_LEN=0x08 and TX_NUM=0x0, bits SPI_RX0[7:0] hold the received data.
     * |        |          |NOTE: The Data Receive Registers are read only registers.
     * |        |          |A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops.
 */
    __I  uint32_t RX1;                   
         uint32_t RESERVE1[2];


    /**
     * TX0
     * ===================================================================================================
     * Offset: 0x20  Data Transmit Register 0
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:31]  |TX        |Data Transmit Register
     * |        |          |The Data Transmit Registers hold the data to be transmitted in the next transfer.
     * |        |          |Valid bit depends on the transmit bit length field in the SPI_CTL register.
     * |        |          |For example, if TX_BIT_LEN=0x08 and the TX_NUM=0x0, the bits SPI_TX0[7:0] will be transmitted in next transfer.
     * |        |          |If TX_BIT_LEN=0x00 and TX_NUM=0x1, H/W will perform two 32-bit transmit/receive successively with the data order {SPI_TX0[31:0], SPI_TX1[31:0]}.
     * |        |          |NOTE: The SPI_RXn and SPI_TXn registers share the same flip-flops, which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI_TXn register between the two transfers.
 */
    __O  uint32_t TX0;                   

    /**
     * TX1
     * ===================================================================================================
     * Offset: 0x24  Data Transmit Register 1
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:31]  |TX        |Data Transmit Register
     * |        |          |The Data Transmit Registers hold the data to be transmitted in the next transfer.
     * |        |          |Valid bit depends on the transmit bit length field in the SPI_CTL register.
     * |        |          |For example, if TX_BIT_LEN=0x08 and the TX_NUM=0x0, the bits SPI_TX0[7:0] will be transmitted in next transfer.
     * |        |          |If TX_BIT_LEN=0x00 and TX_NUM=0x1, H/W will perform two 32-bit transmit/receive successively with the data order {SPI_TX0[31:0], SPI_TX1[31:0]}.
     * |        |          |NOTE: The SPI_RXn and SPI_TXn registers share the same flip-flops, which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI_TXn register between the two transfers.
 */
    __O  uint32_t TX1;                   
         uint32_t RESERVE2[2];


    /**
     * RCLK
     * ===================================================================================================
     * Offset: 0x30  SPI0 Receive Timing Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:1]   |SPI0_FTIM |Fine Timing Control For SPI0 Data Receiving
     * |        |          |The delay timing selected by SPI0_CTIM can be further tuned finely by SPI0_FTIM.
     * |        |          |00 = Receiving data clock of SPI0 has extra 7.5nS delay.
     * |        |          |01 = Receiving data clock of SPI0 has extra 5.0nS delay,.
     * |        |          |10 = Receiving data clock of SPI0 has extra 2.5nS delay,.
     * |        |          |11 = Receiving data clock of SPI0 has no extra delay.
     * |        |          |Note: The extra delay is implemented by delay chains.
     * |        |          |The accuracy of delay time would base on process deviation.
     * |        |          |The default value are set according to the flash controller User Configuration Register CONFIG, SPI0_FTIM=CONFIG[5:4].
     * |[2:3]   |SPI0_CTIM |Coarse Timing Control For SPI0 Data Receiving
     * |        |          |Setting these bits can adjust receiving clock for latching serial-in data correctly in high speed transmission mode.
     * |        |          |00 = Receiving data clock of SPI0 is same as the SPI0_CLK.
     * |        |          |01 = Receiving data clock of SPI0 is delayed 2 half SPI0_CLK clock cycle,.
     * |        |          |10 = Receiving data clock of SPI0 is delayed 3 half SPI0_CLK clock cycle,.
     * |        |          |11 = Receiving data clock of SPI0 is delayed 1 half SPI0_CLK clock cycle ,.
     * |        |          |The default value are set according to the flash controller User Configuration Register CONFIG, SPI0_CTIM=CONFIG[7:6].
 */
    __IO uint32_t RCLK;                  

} SPI_T;

/**
    @addtogroup SPI_CONST SPI Bit Field Definition
    Constant Definitions for SPI Controller
@{ */

#define SPI_CTL_GO_BUSY_Pos              (0)                                               /*!< SPI CTL: GO_BUSY Position              */
#define SPI_CTL_GO_BUSY_Msk              (0x1ul << SPI_CTL_GO_BUSY_Pos)                    /*!< SPI CTL: GO_BUSY Mask                  */

#define SPI_CTL_RX_NEG_Pos               (1)                                               /*!< SPI CTL: RX_NEG Position               */
#define SPI_CTL_RX_NEG_Msk               (0x1ul << SPI_CTL_RX_NEG_Pos)                     /*!< SPI CTL: RX_NEG Mask                   */

#define SPI_CTL_TX_NEG_Pos               (2)                                               /*!< SPI CTL: TX_NEG Position               */
#define SPI_CTL_TX_NEG_Msk               (0x1ul << SPI_CTL_TX_NEG_Pos)                     /*!< SPI CTL: TX_NEG Mask                   */

#define SPI_CTL_DWIDTH_Pos               (3)                                               /*!< SPI CTL: DWIDTH Position           */
#define SPI_CTL_DWIDTH_Msk               (0x1ful << SPI_CTL_DWIDTH_Pos)                    /*!< SPI CTL: DWIDTH Mask               */

#define SPI_CTL_TX_NUM_Pos               (8)                                               /*!< SPI CTL: TX_NUM Position               */
#define SPI_CTL_TX_NUM_Msk               (0x3ul << SPI_CTL_TX_NUM_Pos)                     /*!< SPI CTL: TX_NUM Mask                   */

#define SPI_CTL_LSB_Pos                  (10)                                              /*!< SPI CTL: LSB Position                  */
#define SPI_CTL_LSB_Msk                  (0x1ul << SPI_CTL_LSB_Pos)                        /*!< SPI CTL: LSB Mask                      */

#define SPI_CTL_CLKP_Pos                 (11)                                              /*!< SPI CTL: CLKP Position                 */
#define SPI_CTL_CLKP_Msk                 (0x1ul << SPI_CTL_CLKP_Pos)                       /*!< SPI CTL: CLKP Mask                     */

#define SPI_CTL_SUSPITV_Pos              (12)                                              /*!< SPI CTL: SUSPITV Position                */
#define SPI_CTL_SUSPITV_Msk              (0xful << SPI_CTL_SUSPITV_Pos)                    /*!< SPI CTL: SUSPITV Mask                    */

#define SPI_CTL_UNIT_INTSTS_Pos          (16)                                              /*!< SPI CTL: UNIT_INTSTS Position                */
#define SPI_CTL_UNIT_INTSTS_Msk          (0x1ul << SPI_CTL_UNIT_INTSTS_Pos)                /*!< SPI CTL: UNIT_INTSTS Mask                    */

#define SPI_CTL_UNIT_INTEN_Pos           (17)                                              /*!< SPI CTL: UNIT_INTEN Position                */
#define SPI_CTL_UNIT_INTEN_Msk           (0x1ul << SPI_CTL_UNIT_INTEN_Pos)                 /*!< SPI CTL: UNIT_INTEN Mask                    */

#define SPI_CTL_SLAVE_Pos                (18)                                              /*!< SPI CTL: SLAVE Position                */
#define SPI_CTL_SLAVE_Msk                (0x1ul << SPI_CTL_SLAVE_Pos)                      /*!< SPI CTL: SLAVE Mask                    */

#define SPI_CTL_REORDER_Pos              (20)                                              /*!< SPI CTL: REORDER Position          */
#define SPI_CTL_REORDER_Msk              (0x1ul << SPI_CTL_REORDER_Pos)                    /*!< SPI CTL: REORDER Mask              */

#define SPI_CLKDIV_DIVIDER_Pos           (0)                                               /*!< SPI CLKDIV: DIVIDER Position           */
#define SPI_CLKDIV_DIVIDER_Msk           (0xfffful << SPI_CLKDIV_DIVIDER_Pos)              /*!< SPI CLKDIV: DIVIDER Mask               */

#define SPI_SSCTL_SS_Pos                 (0)                                               /*!< SPI SSCTL: SS Position               */
#define SPI_SSCTL_SS_Msk                 (0x3ul << SPI_SSCTL_SS_Pos)                       /*!< SPI SSCTL: SS Mask                   */

#define SPI_SSCTL_SS_LVL_Pos             (2)                                               /*!< SPI SSCTL: SS_LVL Position             */
#define SPI_SSCTL_SS_LVL_Msk             (0x1ul << SPI_SSCTL_SS_LVL_Pos)                   /*!< SPI SSCTL: SS_LVL Mask                 */

#define SPI_SSCTL_AUTOSS_Pos             (3)                                               /*!< SPI SSCTL: AUTOSS Position                */
#define SPI_SSCTL_AUTOSS_Msk             (0x1ul << SPI_SSCTL_AUTOSS_Pos)                   /*!< SPI SSCTL: AUTOSS Mask                    */

#define SPI_SSCTL_SS_LTRIG_Pos           (4)                                               /*!< SPI SSCTL: SS_LTRIG Position           */
#define SPI_SSCTL_SS_LTRIG_Msk           (0x1ul << SPI_SSCTL_SS_LTRIG_Pos)                 /*!< SPI SSCTL: SS_LTRIG Mask               */

#define SPI_SSCTL_LTRIG_FLAG_Pos         (5)                                               /*!< SPI SSCTL: LTRIG_FLAG Position         */
#define SPI_SSCTL_LTRIG_FLAG_Msk         (0x1ul << SPI_SSCTL_LTRIG_FLAG_Pos)               /*!< SPI SSCTL: LTRIG_FLAG Mask             */

#define SPI_RX0_RX_Pos                   (0)                                               /*!< SPI RX0: RX Position                   */
#define SPI_RX0_RX_Msk                   (0xfffffffful << SPI_RX0_RX_Pos)                  /*!< SPI RX0: RX Mask                       */

#define SPI_RX1_RX_Pos                   (0)                                               /*!< SPI RX1: RX Position                   */
#define SPI_RX1_RX_Msk                   (0xfffffffful << SPI_RX1_RX_Pos)                  /*!< SPI RX1: RX Mask                       */

#define SPI_TX0_TX_Pos                   (0)                                               /*!< SPI TX0: TX Position                   */
#define SPI_TX0_TX_Msk                   (0xfffffffful << SPI_TX0_TX_Pos)                  /*!< SPI TX0: TX Mask                       */

#define SPI_TX1_TX_Pos                   (0)                                               /*!< SPI TX1: TX Position                   */
#define SPI_TX1_TX_Msk                   (0xfffffffful << SPI_TX1_TX_Pos)                  /*!< SPI TX1: TX Mask                       */

#define SPI_RCLK_SPI0_FTIM_Pos           (0)                                               /*!< SPI RCLK: SPI0_FTIM Position           */
#define SPI_RCLK_SPI0_FTIM_Msk           (0x3ul << SPI_RCLK_SPI0_FTIM_Pos)                 /*!< SPI RCLK: SPI0_FTIM Mask               */

#define SPI_RCLK_SPI0_CTIM_Pos           (2)                                               /*!< SPI RCLK: SPI0_CTIM Position           */
#define SPI_RCLK_SPI0_CTIM_Msk           (0x3ul << SPI_RCLK_SPI0_CTIM_Pos)                 /*!< SPI RCLK: SPI0_CTIM Mask               */

/**@}*/ /* SPI_CONST */
/**@}*/ /* end of SPI register group */


/*---------------------- System Manger Controller -------------------------*/
/**
    @addtogroup SYS System Manger Controller(SYS)
    Memory Mapped Structure for SYS Controller
@{ */
 
typedef struct
{


    /**
     * PDID
     * ===================================================================================================
     * Offset: 0x00  Product Identifier Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:31]  |PDID      |Product Identifier
     * |        |          |Chip identifier (part number) for N572F072/N572P072 series.
 */
    __I  uint32_t PDID;                  

    /**
     * RSTSTS
     * ===================================================================================================
     * Offset: 0x04  System Reset Source Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |PORF      |POR Reset Flag
     * |        |          |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller to indicate the previous reset source.
     * |        |          |0 = No reset from POR.
     * |        |          |1 = Power-on Reset (POR) Controller had issued the reset signal to reset the system.
     * |        |          |Note: Write 1 to clear this bit to 0. 
     * |[1]     |PINRF     |NRESET Pin Reset Flag
     * |        |          |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
     * |        |          |0 = No reset from nRESET pin.
     * |        |          |1 = Pin nRESET had issued the reset signal to reset the system.
     * |        |          |Note: Write 1 to clear this bit to 0. 
     * |[2]     |WDTRF     |Reset Source From WDG
     * |        |          |The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.
     * |        |          |0= No reset from Watch-Dog.
     * |        |          |1= The Watch-Dog module issued the reset signal to reset the system.
     * |        |          |Note: Write 1 to clear this bit to 0.
     * |[3]     |LVRF      |LVR Reset Flag
     * |        |          |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source.
     * |        |          |0 = No reset from LVR.
     * |        |          |1 = LVR controller had issued the reset signal to reset the system.
     * |        |          |Note: Write 1 to clear this bit to 0.
     * |[6]     |PMURSTF   |Reset Source From PMU
     * |        |          |The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source.
     * |        |          |0= No reset from PMU.
     * |        |          |1= The PMU has issued the reset signal to reset the system.
     * |        |          |Note: Write 1 to clear this bit to 0.
 */
    __IO uint32_t RSTSTS;                

    /**
     * IPRST0
     * ===================================================================================================
     * Offset: 0x08  IP Reset Control Resister0
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |CHIPRST   |CHIP One Shot Reset
     * |        |          |Set this bit will reset the whole chip, this bit will automatically return to "0" after 2 clock cycles.
     * |        |          |CHIPRST has same behavior as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded.
     * |        |          |0 = Normal.
     * |        |          |1 = Reset CHIP.
     * |[1]     |CPURST    |CPU Kernel One Shot Reset
     * |        |          |Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to "0" after the 2 clock cycles
     * |        |          |0 = Normal.
     * |        |          |1 = Reset CPU.
     * |[2]     |CPUWS     |CPU Wait-State Control For Flash Memory Access
     * |        |          |0 = 1 HCLK clock wait-state.
     * |        |          |1 = zero wait-state.
     * |        |          |Note: that CPUWS cannot be set as "1" when CPU runs the program to do Flash ISP operation.
     * |[3]     |RAMWS     |Wait State Control For CPU Access RAM
     * |        |          |0 = 1 HCLK clock wait-state.
     * |        |          |1 = zero wait-state.
 */
    __IO uint32_t IPRST0;                

    /**
     * IPRST1
     * ===================================================================================================
     * Offset: 0x0C  IP Reset Control Resister1
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[1]     |GPIORST   |GPIO Controller Reset
     * |        |          |0 = Normal operation.
     * |        |          |1 = Reset.
     * |[2]     |TMR0RST   |Timer0 Controller Reset
     * |        |          |0 = Normal Operation.
     * |        |          |1 = Reset.
     * |[3]     |TMR1RST   |Timer1 Controller Reset
     * |        |          |0 = Normal Operation.
     * |        |          |1 = Reset.
     * |[4]     |TMR2RST   |Timer2 Controller Reset
     * |        |          |0 = Normal operation.
     * |        |          |1 = Reset.
     * |[5]     |APURST    |APU Controller Reset
     * |        |          |0 = Normal operation.
     * |        |          |1 = Reset.
     * |[6]     |TMRFRST   |TimerF Controller Reset
     * |        |          |0 = Normal operation.
     * |        |          |1 = Reset.
     * |[12]    |SPI0RST   |SPI0 Controller Reset
     * |        |          |0 = Normal Operation.
     * |        |          |1 = Reset.
     * |[13]    |SPI1RST   |SPI1 Controller Reset
     * |        |          |0 = Normal Operation.
     * |        |          |1 = Reset.
     * |[20]    |PWMRST    |PWM Controller Reset
     * |        |          |0 = Normal Operation.
     * |        |          |1 = Reset.
     * |[28]    |ADCRST    |ADC Controller Reset
     * |        |          |0 = Normal Operation.
     * |        |          |1 = Reset.
 */
    __IO uint32_t IPRST1;                
         uint32_t RESERVE0[2];


    /**
     * BODCTL
     * ===================================================================================================
     * Offset: 0x18  Brown-Out Detector Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |BOD_EN    |Brown-Out Detector Enable (Initiated & Protected Bit)
     * |        |          |The default value is set according to the flash controller User Configuration Register CONFIG[23], BOD_EN = ~CONFIG[23].
     * |        |          |0 = Brown-Out Detector function is disabled.
     * |        |          |1 = Brown-Out Detector function is enabled,.
     * |[1]     |BOD_VL    |Brown-Out Detector Threshold Voltage Selection (Initiate & Protected Bit)
     * |        |          |The default value is set by flash controller user configuration register CONFIG[21].
     * |        |          |BOD_VL
     * |        |          |Threshold   voltage
     * |        |          |1
     * |        |          |3.0V
     * |        |          |0
     * |        |          |2.7V
     * |[6]     |BOD_OUT   |The Status For Brown-Out Detector Output It's a read only bit.
     * |        |          |0 = The detected voltage is lower than BOD_VL setting.
     * |        |          |If the BOD_EN is "0", this bit always responses "0".
     * |        |          |1 = The detected voltage is higher than BOD_VL setting.
     * |[7]     |LVR_EN    |Low Voltage Reset (LVR) Enable (Protected Bit)
     * |        |          |The LVR function resets the chip when the input power voltage is lower
     * |        |          |than LVR circuit setting. LVR function is enabled in default.
     * |        |          |0 = Disable LVR function.
     * |        |          |1 = Enable LVR function - After enable the bit, the LVR function will active with 100uS delay for LVR output stable.
 */
    __IO uint32_t BODCTL;                

    /**
     * PORCTL
     * ===================================================================================================
     * Offset: 0x1C  Power-On-Reset Controller Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |POROFF    |Power-On Reset Enable Bit (Write Protect)
     * |        |          |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
     * |        |          |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
     * |        |          |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
     * |        |          |nRESET, Watchdog, LVR reset, ICE reset command and the software-chip reset function. 
 */
    __IO uint32_t PORCTL;                
         uint32_t RESERVE1[4];


    /**
     * GPA_MFP
     * ===================================================================================================
     * Offset: 0x30  GPIO PA Multiple Alternate Functions and Input Type Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |PA0MFP    |0 = The GPIOA-0 is selected to the pin PA.0.
     * |        |          |1 = SPI0 2nd chip select output.
     * |[1]     |PA1MFP    |0 = The GPIOA-1 is selected to the pin PA.1.
     * |        |          |1 = SPI0 1st chip select output.
     * |[2]     |PA2MFP    |0 = The GPIOA-2 is selected to the pin PA.2.
     * |        |          |1 = SPI0 clock output.
     * |[3]     |PA3MFP    |0 = The GPIOA-3 is selected to the pin PA.3.
     * |        |          |1 = SPI0 data input.
     * |[4]     |PA4MFP    |0 = The GPIOA-4 is selected to the pin PA.4.
     * |        |          |1 = SPI0 data output.
     * |[5]     |PA5MFP    |0 = The GPIOA-5 is selected to the pin PA.5.
     * |        |          |1 = Timer0 counter external input.
     * |[6]     |PA6MFP    |0 = The GPIOA-6 is selected to the pin PA.6.
     * |        |          |1 = External interrupt input.
     * |[7]     |PA7MFP    |0 = The GPIOA-7 is selected to the pin PA.7.
     * |        |          |1 = ADC input external trigger input.
     * |[8]     |PA8MFP    |0 = The GPIOA-8 is selected to the pin PA.8.
     * |        |          |1 = ADC input channel 0.
     * |[9]     |PA9MFP    |0 = The GPIOA-9 is selected to the pin PA.9.
     * |        |          |1 = ADC input channel 1.
     * |[10]    |PA10MFP   |0 = The GPIOA-10 is selected to the pin PA.10.
     * |        |          |1 = ADC input channel 2.
     * |[11]    |PA11MFP   |0 = The GPIOA-11 is selected to the pin PA.11.
     * |        |          |1 = ADC input channel 3.
     * |[12]    |PA12MFP   |0 = The GPIOA-12 is selected to the pin PA.12.
     * |        |          |1 = ADC input channel 4.
     * |[13]    |PA13MFP   |0 = The GPIOA-13 is selected to the pin PA.13.
     * |        |          |1 = ADC input channel 5.
     * |[14]    |PA14MFP   |0 = The GPIOA-14 is selected to the pin PA.14.
     * |        |          |1 = ADC input channel 6.
     * |[15]    |PA15MFP   |0 = The GPIOA-15 is selected to the pin PA.15.
     * |        |          |1 = ADC input channel 7.
     * |[16:31] |PAnTYPEn  |0 = PA.n I/O cell input Schmitt Trigger function is disabled.
     * |        |          |1 = PA.n I/O cell input Schmitt Trigger function is enabled.
 */
    __IO uint32_t GPA_MFP;               

    /**
     * GPB_MFP
     * ===================================================================================================
     * Offset: 0x34  GPIO PB Multiple Alternate Functions and Input Type Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |PB0MFP    |0 = The GPIOB-0 is selected to the pin PB.0.
     * |        |          |1 = SPI1 2nd chip select output.
     * |[1]     |PB1MFP    |0 = The GPIOB-1 is selected to the pin PB.1.
     * |        |          |1 = SPI1 1st chip select output or slave select input.
     * |[2]     |PB2MFP    |0 = The GPIOB-2 is selected to the pin PB.2.
     * |        |          |1 = SPI1 clock output/input.
     * |[3]     |PB3MFP    |0 = The GPIOB-3 is selected to the pin PB.3.
     * |        |          |1 = SPI1 data input/output.
     * |[4]     |PB4MFP    |0 = The GPIOB-4 is selected to the pin PB.4.
     * |        |          |1 = SPI1 data output/input.
     * |[8]     |PB8MFP    |0 = The GPIOB-8 is selected to the pin PB.8.
     * |        |          |1 = PWM output pin 0.
     * |[9]     |PB9MFP    |0 = The GPIOB-9 is selected to the pin PB.9.
     * |        |          |1 = PWM output pin 1.
     * |[10]    |PB10MFP   |0 = The GPIOB-10 is selected to the pin PB.10.
     * |        |          |1 = PWM output pin 2.
     * |[11]    |PB11MFP   |0 = The GPIOB-11 is selected to the pin PB.11.
     * |        |          |1 = PWM output pin 3.
     * |[12]    |PB12MFP   |0 = The GPIOB-12 is selected to the pin PB.12.
     * |        |          |1 = PWM timer capture input.
     * |[13]    |PB13MFP   |0 = The GPIOB-13 is selected to the pin PB.13.
     * |        |          |1 = IR carrier output.
     * |[14]    |PB14MFP   |0 = The GPIOB-14 is selected to the pin PB.14.
     * |        |          |1 = Timer1 counter external input.
     * |[15]    |PB15MFP   |0 = The GPIOB-15 is selected to the pin PB.15.
     * |        |          |1 = Timer2 counter external input.
     * |[16:31] |PBnTYPEn  |0 = PB.n I/O cell input Schmitt Trigger function is disabled.
     * |        |          |1 = PB.n I/O cell input Schmitt Trigger function is enabled.
 */
    __IO uint32_t GPB_MFP;               

    /**
     * GPA_HS
     * ===================================================================================================
     * Offset: 0x38  PA.4 ~ PA.0 High Speed Transition Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:4]   |GPA_HS    |GPA_HS[n] =0: PA.n I/O is normal speed (less than 15MHz) transition.
     * |        |          | =1: PA.n I/O is high speed (up to 48MHz) transition.
     * |        |          |(n=0~4).
     * |[16:20] |GPRB      |Five general purpose R/W register bits.
 */
    __IO uint32_t GPA_HS;                
         uint32_t RESERVE2[49];


    /**
     * REGLCTL
     * ===================================================================================================
     * Offset: 0x100  Register Lock Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |REGLCTL   |Protected Register Lock/Unlock Index (Read Only)
     * |        |          |0 = Protected registers are locked. Any write to the target register is ignored.
     * |        |          |1 = Protected registers are unlocked.
     * |        |          |The protected registers are:
     * |        |          |SYS_IPRST0 - address 0x5000_0008
     * |        |          |SYS_BODCTL - address 0x5000_0018
     * |        |          |SYS_PORCTL - address 0x5000_001C
     * |        |          |CLK_PWRCTL - address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear)
     * |        |          |CLK_APBCLK bit[0] - address 0x5000_0208 (bit[0] is watch dog clock enable)
     * |        |          |CLK_CLKSEL0 - address 0x5000_0210 (for HCLK clock source select)
     * |        |          |CLK_CLKSEL1 -- address 0x5000_0214 (bit[1:0] is watch dog clock selection)
     * |        |          |NMI_SEL[7]= IRQ_TM - address 0x5000_0380.
     * |        |          |SPI0_RCLK - address 0x4003_0030
     * |        |          |FMC_ISPCTL -- address 0x5000_C000 (Flash ISP Control register)
     * |        |          |WDT_CTL -- address 0x4000_4000
     * |[0:7]   |SYS_REGLCTL|Register Lock Control Code (Write Only)
     * |        |          |Some registers have write-protection function.
     * |        |          |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
     * |        |          |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
 */
    __IO  uint32_t REGLCTL;               

} SYS_T;

/**
    @addtogroup SYS_CONST SYS Bit Field Definition
    Constant Definitions for SYS Controller
@{ */

#define SYS_PDID_PDID_Pos                (0)                                               /*!< SYS PDID: PDID Position                */
#define SYS_PDID_PDID_Msk                (0xfffffffful << SYS_PDID_PDID_Pos)               /*!< SYS PDID: PDID Mask                    */

#define SYS_RSTSTS_PORF_Pos              (0)                                               /*!< SYS RSTSTS: PORF Position              */
#define SYS_RSTSTS_PORF_Msk              (0x1ul << SYS_RSTSTS_PORF_Pos)                    /*!< SYS RSTSTS: PORF Mask                  */

#define SYS_RSTSTS_PINRF_Pos             (1)                                               /*!< SYS RSTSTS: PINRF Position             */
#define SYS_RSTSTS_PINRF_Msk             (0x1ul << SYS_RSTSTS_PINRF_Pos)                   /*!< SYS RSTSTS: PINRF Mask                 */

#define SYS_RSTSTS_WDTRF_Pos             (2)                                               /*!< SYS RSTSTS: WDTRF Position             */
#define SYS_RSTSTS_WDTRF_Msk             (0x1ul << SYS_RSTSTS_WDTRF_Pos)                   /*!< SYS RSTSTS: WDTRF Mask                 */

#define SYS_RSTSTS_LVRF_Pos              (3)                                               /*!< SYS RSTSTS: LVRF Position              */
#define SYS_RSTSTS_LVRF_Msk              (0x1ul << SYS_RSTSTS_LVRF_Pos)                    /*!< SYS RSTSTS: LVRF Mask                  */

#define SYS_RSTSTS_PMURSTF_Pos           (6)                                               /*!< SYS RSTSTS: PMURSTF Position           */
#define SYS_RSTSTS_PMURSTF_Msk           (0x1ul << SYS_RSTSTS_PMURSTF_Pos)                 /*!< SYS RSTSTS: PMURSTF Mask               */

#define SYS_IPRST0_CHIPRST_Pos           (0)                                               /*!< SYS IPRST0: CHIPRST Position           */
#define SYS_IPRST0_CHIPRST_Msk           (0x1ul << SYS_IPRST0_CHIPRST_Pos)                 /*!< SYS IPRST0: CHIPRST Mask               */

#define SYS_IPRST0_CPURST_Pos            (1)                                               /*!< SYS IPRST0: CPURST Position            */
#define SYS_IPRST0_CPURST_Msk            (0x1ul << SYS_IPRST0_CPURST_Pos)                  /*!< SYS IPRST0: CPURST Mask                */

#define SYS_IPRST0_CPUWS_Pos             (2)                                               /*!< SYS IPRST0: CPUWS Position             */
#define SYS_IPRST0_CPUWS_Msk             (0x1ul << SYS_IPRST0_CPUWS_Pos)                   /*!< SYS IPRST0: CPUWS Mask                 */

#define SYS_IPRST0_RAMWS_Pos             (3)                                               /*!< SYS IPRST0: RAMWS Position             */
#define SYS_IPRST0_RAMWS_Msk             (0x1ul << SYS_IPRST0_RAMWS_Pos)                   /*!< SYS IPRST0: RAMWS Mask                 */

#define SYS_IPRST1_GPIORST_Pos           (1)                                               /*!< SYS IPRST1: GPIORST Position           */
#define SYS_IPRST1_GPIORST_Msk           (0x1ul << SYS_IPRST1_GPIORST_Pos)                 /*!< SYS IPRST1: GPIORST Mask               */

#define SYS_IPRST1_TMR0RST_Pos           (2)                                               /*!< SYS IPRST1: TMR0RST Position           */
#define SYS_IPRST1_TMR0RST_Msk           (0x1ul << SYS_IPRST1_TMR0RST_Pos)                 /*!< SYS IPRST1: TMR0RST Mask               */

#define SYS_IPRST1_TMR1RST_Pos           (3)                                               /*!< SYS IPRST1: TMR1RST Position           */
#define SYS_IPRST1_TMR1RST_Msk           (0x1ul << SYS_IPRST1_TMR1RST_Pos)                 /*!< SYS IPRST1: TMR1RST Mask               */

#define SYS_IPRST1_TMR2RST_Pos           (4)                                               /*!< SYS IPRST1: TMR2RST Position           */
#define SYS_IPRST1_TMR2RST_Msk           (0x1ul << SYS_IPRST1_TMR2RST_Pos)                 /*!< SYS IPRST1: TMR2RST Mask               */

#define SYS_IPRST1_APURST_Pos            (5)                                               /*!< SYS IPRST1: APURST Position            */
#define SYS_IPRST1_APURST_Msk            (0x1ul << SYS_IPRST1_APURST_Pos)                  /*!< SYS IPRST1: APURST Mask                */

#define SYS_IPRST1_TMRFRST_Pos           (6)                                               /*!< SYS IPRST1: TMRFRST Position           */
#define SYS_IPRST1_TMRFRST_Msk           (0x1ul << SYS_IPRST1_TMRFRST_Pos)                 /*!< SYS IPRST1: TMRFRST Mask               */

#define SYS_IPRST1_SPI0RST_Pos           (12)                                              /*!< SYS IPRST1: SPI0RST Position           */
#define SYS_IPRST1_SPI0RST_Msk           (0x1ul << SYS_IPRST1_SPI0RST_Pos)                 /*!< SYS IPRST1: SPI0RST Mask               */

#define SYS_IPRST1_SPI1RST_Pos           (13)                                              /*!< SYS IPRST1: SPI1RST Position           */
#define SYS_IPRST1_SPI1RST_Msk           (0x1ul << SYS_IPRST1_SPI1RST_Pos)                 /*!< SYS IPRST1: SPI1RST Mask               */

#define SYS_IPRST1_PWMRST_Pos            (20)                                              /*!< SYS IPRST1: PWMRST Position            */
#define SYS_IPRST1_PWMRST_Msk            (0x1ul << SYS_IPRST1_PWMRST_Pos)                  /*!< SYS IPRST1: PWMRST Mask                */

#define SYS_IPRST1_ADCRST_Pos            (28)                                              /*!< SYS IPRST1: ADCRST Position            */
#define SYS_IPRST1_ADCRST_Msk            (0x1ul << SYS_IPRST1_ADCRST_Pos)                  /*!< SYS IPRST1: ADCRST Mask                */

#define SYS_BODCTL_BOD_EN_Pos            (0)                                               /*!< SYS BODCTL: BOD_EN Position            */
#define SYS_BODCTL_BOD_EN_Msk            (0x1ul << SYS_BODCTL_BOD_EN_Pos)                  /*!< SYS BODCTL: BOD_EN Mask                */

#define SYS_BODCTL_BOD_VL_Pos            (1)                                               /*!< SYS BODCTL: BOD_VL Position            */
#define SYS_BODCTL_BOD_VL_Msk            (0x1ul << SYS_BODCTL_BOD_VL_Pos)                  /*!< SYS BODCTL: BOD_VL Mask                */

#define SYS_BODCTL_BOD_OUT_Pos           (6)                                               /*!< SYS BODCTL: BOD_OUT Position           */
#define SYS_BODCTL_BOD_OUT_Msk           (0x1ul << SYS_BODCTL_BOD_OUT_Pos)                 /*!< SYS BODCTL: BOD_OUT Mask               */

#define SYS_BODCTL_LVR_EN_Pos            (7)                                               /*!< SYS BODCTL: LVR_EN Position            */
#define SYS_BODCTL_LVR_EN_Msk            (0x1ul << SYS_BODCTL_LVR_EN_Pos)                  /*!< SYS BODCTL: LVR_EN Mask                */

#define SYS_PORCTL_POROFF_Pos            (0)                                               /*!< SYS PORCTL: POROFF Position            */
#define SYS_PORCTL_POROFF_Msk            (0xfffful << SYS_PORCTL_POROFF_Pos)               /*!< SYS PORCTL: POROFF Mask                */

#define SYS_GPA_MFP_PA0MFP_Pos           (0)                                               /*!< SYS GPA_MFP: PA0MFP Position           */
#define SYS_GPA_MFP_PA0MFP_Msk           (0x1ul << SYS_GPA_MFP_PA0MFP_Pos)                 /*!< SYS GPA_MFP: PA0MFP Mask               */

#define SYS_GPA_MFP_PA1MFP_Pos           (1)                                               /*!< SYS GPA_MFP: PA1MFP Position           */
#define SYS_GPA_MFP_PA1MFP_Msk           (0x1ul << SYS_GPA_MFP_PA1MFP_Pos)                 /*!< SYS GPA_MFP: PA1MFP Mask               */

#define SYS_GPA_MFP_PA2MFP_Pos           (2)                                               /*!< SYS GPA_MFP: PA2MFP Position           */
#define SYS_GPA_MFP_PA2MFP_Msk           (0x1ul << SYS_GPA_MFP_PA2MFP_Pos)                 /*!< SYS GPA_MFP: PA2MFP Mask               */

#define SYS_GPA_MFP_PA3MFP_Pos           (3)                                               /*!< SYS GPA_MFP: PA3MFP Position           */
#define SYS_GPA_MFP_PA3MFP_Msk           (0x1ul << SYS_GPA_MFP_PA3MFP_Pos)                 /*!< SYS GPA_MFP: PA3MFP Mask               */

#define SYS_GPA_MFP_PA4MFP_Pos           (4)                                               /*!< SYS GPA_MFP: PA4MFP Position           */
#define SYS_GPA_MFP_PA4MFP_Msk           (0x1ul << SYS_GPA_MFP_PA4MFP_Pos)                 /*!< SYS GPA_MFP: PA4MFP Mask               */

#define SYS_GPA_MFP_PA5MFP_Pos           (5)                                               /*!< SYS GPA_MFP: PA5MFP Position           */
#define SYS_GPA_MFP_PA5MFP_Msk           (0x1ul << SYS_GPA_MFP_PA5MFP_Pos)                 /*!< SYS GPA_MFP: PA5MFP Mask               */

#define SYS_GPA_MFP_PA6MFP_Pos           (6)                                               /*!< SYS GPA_MFP: PA6MFP Position           */
#define SYS_GPA_MFP_PA6MFP_Msk           (0x1ul << SYS_GPA_MFP_PA6MFP_Pos)                 /*!< SYS GPA_MFP: PA6MFP Mask               */

#define SYS_GPA_MFP_PA7MFP_Pos           (7)                                               /*!< SYS GPA_MFP: PA7MFP Position           */
#define SYS_GPA_MFP_PA7MFP_Msk           (0x1ul << SYS_GPA_MFP_PA7MFP_Pos)                 /*!< SYS GPA_MFP: PA7MFP Mask               */

#define SYS_GPA_MFP_PA8MFP_Pos           (8)                                               /*!< SYS GPA_MFP: PA8MFP Position           */
#define SYS_GPA_MFP_PA8MFP_Msk           (0x1ul << SYS_GPA_MFP_PA8MFP_Pos)                 /*!< SYS GPA_MFP: PA8MFP Mask               */

#define SYS_GPA_MFP_PA9MFP_Pos           (9)                                               /*!< SYS GPA_MFP: PA9MFP Position           */
#define SYS_GPA_MFP_PA9MFP_Msk           (0x1ul << SYS_GPA_MFP_PA9MFP_Pos)                 /*!< SYS GPA_MFP: PA9MFP Mask               */

#define SYS_GPA_MFP_PA10MFP_Pos          (10)                                              /*!< SYS GPA_MFP: PA10MFP Position          */
#define SYS_GPA_MFP_PA10MFP_Msk          (0x1ul << SYS_GPA_MFP_PA10MFP_Pos)                /*!< SYS GPA_MFP: PA10MFP Mask              */

#define SYS_GPA_MFP_PA11MFP_Pos          (11)                                              /*!< SYS GPA_MFP: PA11MFP Position          */
#define SYS_GPA_MFP_PA11MFP_Msk          (0x1ul << SYS_GPA_MFP_PA11MFP_Pos)                /*!< SYS GPA_MFP: PA11MFP Mask              */

#define SYS_GPA_MFP_PA12MFP_Pos          (12)                                              /*!< SYS GPA_MFP: PA12MFP Position          */
#define SYS_GPA_MFP_PA12MFP_Msk          (0x1ul << SYS_GPA_MFP_PA12MFP_Pos)                /*!< SYS GPA_MFP: PA12MFP Mask              */

#define SYS_GPA_MFP_PA13MFP_Pos          (13)                                              /*!< SYS GPA_MFP: PA13MFP Position          */
#define SYS_GPA_MFP_PA13MFP_Msk          (0x1ul << SYS_GPA_MFP_PA13MFP_Pos)                /*!< SYS GPA_MFP: PA13MFP Mask              */

#define SYS_GPA_MFP_PA14MFP_Pos          (14)                                              /*!< SYS GPA_MFP: PA14MFP Position          */
#define SYS_GPA_MFP_PA14MFP_Msk          (0x1ul << SYS_GPA_MFP_PA14MFP_Pos)                /*!< SYS GPA_MFP: PA14MFP Mask              */

#define SYS_GPA_MFP_PA15MFP_Pos          (15)                                              /*!< SYS GPA_MFP: PA15MFP Position          */
#define SYS_GPA_MFP_PA15MFP_Msk          (0x1ul << SYS_GPA_MFP_PA15MFP_Pos)                /*!< SYS GPA_MFP: PA15MFP Mask              */

#define SYS_GPA_MFP_PAnTYPEn_Pos         (16)                                              /*!< SYS GPA_MFP: PAnTYPEn Position         */
#define SYS_GPA_MFP_PAnTYPEn_Msk         (0xfffful << SYS_GPA_MFP_PAnTYPEn_Pos)            /*!< SYS GPA_MFP: PAnTYPEn Mask             */

#define SYS_GPB_MFP_PB0MFP_Pos           (0)                                               /*!< SYS GPB_MFP: PB0MFP Position           */
#define SYS_GPB_MFP_PB0MFP_Msk           (0x1ul << SYS_GPB_MFP_PB0MFP_Pos)                 /*!< SYS GPB_MFP: PB0MFP Mask               */

#define SYS_GPB_MFP_PB1MFP_Pos           (1)                                               /*!< SYS GPB_MFP: PB1MFP Position           */
#define SYS_GPB_MFP_PB1MFP_Msk           (0x1ul << SYS_GPB_MFP_PB1MFP_Pos)                 /*!< SYS GPB_MFP: PB1MFP Mask               */

#define SYS_GPB_MFP_PB2MFP_Pos           (2)                                               /*!< SYS GPB_MFP: PB2MFP Position           */
#define SYS_GPB_MFP_PB2MFP_Msk           (0x1ul << SYS_GPB_MFP_PB2MFP_Pos)                 /*!< SYS GPB_MFP: PB2MFP Mask               */

#define SYS_GPB_MFP_PB3MFP_Pos           (3)                                               /*!< SYS GPB_MFP: PB3MFP Position           */
#define SYS_GPB_MFP_PB3MFP_Msk           (0x1ul << SYS_GPB_MFP_PB3MFP_Pos)                 /*!< SYS GPB_MFP: PB3MFP Mask               */

#define SYS_GPB_MFP_PB4MFP_Pos           (4)                                               /*!< SYS GPB_MFP: PB4MFP Position           */
#define SYS_GPB_MFP_PB4MFP_Msk           (0x1ul << SYS_GPB_MFP_PB4MFP_Pos)                 /*!< SYS GPB_MFP: PB4MFP Mask               */

#define SYS_GPB_MFP_PB8MFP_Pos           (8)                                               /*!< SYS GPB_MFP: PB8MFP Position           */
#define SYS_GPB_MFP_PB8MFP_Msk           (0x1ul << SYS_GPB_MFP_PB8MFP_Pos)                 /*!< SYS GPB_MFP: PB8MFP Mask               */

#define SYS_GPB_MFP_PB9MFP_Pos           (9)                                               /*!< SYS GPB_MFP: PB9MFP Position           */
#define SYS_GPB_MFP_PB9MFP_Msk           (0x1ul << SYS_GPB_MFP_PB9MFP_Pos)                 /*!< SYS GPB_MFP: PB9MFP Mask               */

#define SYS_GPB_MFP_PB10MFP_Pos          (10)                                              /*!< SYS GPB_MFP: PB10MFP Position          */
#define SYS_GPB_MFP_PB10MFP_Msk          (0x1ul << SYS_GPB_MFP_PB10MFP_Pos)                /*!< SYS GPB_MFP: PB10MFP Mask              */

#define SYS_GPB_MFP_PB11MFP_Pos          (11)                                              /*!< SYS GPB_MFP: PB11MFP Position          */
#define SYS_GPB_MFP_PB11MFP_Msk          (0x1ul << SYS_GPB_MFP_PB11MFP_Pos)                /*!< SYS GPB_MFP: PB11MFP Mask              */

#define SYS_GPB_MFP_PB12MFP_Pos          (12)                                              /*!< SYS GPB_MFP: PB12MFP Position          */
#define SYS_GPB_MFP_PB12MFP_Msk          (0x1ul << SYS_GPB_MFP_PB12MFP_Pos)                /*!< SYS GPB_MFP: PB12MFP Mask              */

#define SYS_GPB_MFP_PB13MFP_Pos          (13)                                              /*!< SYS GPB_MFP: PB13MFP Position          */
#define SYS_GPB_MFP_PB13MFP_Msk          (0x1ul << SYS_GPB_MFP_PB13MFP_Pos)                /*!< SYS GPB_MFP: PB13MFP Mask              */

#define SYS_GPB_MFP_PB14MFP_Pos          (14)                                              /*!< SYS GPB_MFP: PB14MFP Position          */
#define SYS_GPB_MFP_PB14MFP_Msk          (0x1ul << SYS_GPB_MFP_PB14MFP_Pos)                /*!< SYS GPB_MFP: PB14MFP Mask              */

#define SYS_GPB_MFP_PB15MFP_Pos          (15)                                              /*!< SYS GPB_MFP: PB15MFP Position          */
#define SYS_GPB_MFP_PB15MFP_Msk          (0x1ul << SYS_GPB_MFP_PB15MFP_Pos)                /*!< SYS GPB_MFP: PB15MFP Mask              */

#define SYS_GPB_MFP_PBnTYPEn_Pos         (16)                                              /*!< SYS GPB_MFP: PBnTYPEn Position         */
#define SYS_GPB_MFP_PBnTYPEn_Msk         (0xfffful << SYS_GPB_MFP_PBnTYPEn_Pos)            /*!< SYS GPB_MFP: PBnTYPEn Mask             */

#define SYS_GPA_HS_GPA_HS_Pos            (0)                                               /*!< SYS GPA_HS: GPA_HS Position            */
#define SYS_GPA_HS_GPA_HS_Msk            (0x1ful << SYS_GPA_HS_GPA_HS_Pos)                 /*!< SYS GPA_HS: GPA_HS Mask                */

#define SYS_GPA_HS_GPRB_Pos              (16)                                              /*!< SYS GPA_HS: GPRB Position              */
#define SYS_GPA_HS_GPRB_Msk              (0x1ful << SYS_GPA_HS_GPRB_Pos)                   /*!< SYS GPA_HS: GPRB Mask                  */

#define SYS_REGLCTL_REGLCTL_Pos          (0)                                               /*!< SYS REGLCTL: REGLCTL Position          */
#define SYS_REGLCTL_REGLCTL_Msk          (0x1ul << SYS_REGLCTL_REGLCTL_Pos)                /*!< SYS REGLCTL: REGLCTL Mask              */

#define SYS_REGLCTL_SYS_REGLCTL_Pos      (0)                                               /*!< SYS REGLCTL: SYS_REGLCTL Position      */
#define SYS_REGLCTL_SYS_REGLCTL_Msk      (0xfful << SYS_REGLCTL_SYS_REGLCTL_Pos)           /*!< SYS REGLCTL: SYS_REGLCTL Mask          */

/**@}*/ /* SYS_CONST */
/**@}*/ /* end of SYS register group */


/*---------------------- Timer Controller -------------------------*/
/**
    @addtogroup TMR Timer Controller(TMR)
    Memory Mapped Structure for TMR Controller
@{ */
 
typedef struct
{


    /**
     * CTL
     * ===================================================================================================
     * Offset: 0x00  Timer Control and Status Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:7]   |PSC       |Timer Clock Prescaler
     * |        |          |Clock input is divided by (PSC+1) before it is fed to the counter.
     * |        |          |If PSC = 0, then there is no scaling.
     * |[25]    |ACTSTS    |Timer Active Status Bit (Read Only)
     * |        |          |This bit indicates the counter status of Timer.
     * |        |          |0 = Timer is not active.
     * |        |          |1 = Timer is active.
     * |[26]    |RSTCNT    |Counter Reset Bit
     * |        |          |Set this bit will reset the Timer counter, pre-scale and also force CNTEN to 0.
     * |        |          |0 = No effect.
     * |        |          |1 = Reset Timer's pre-scale counter, internal 16-bit up-counter and CNTEN bit.
     * |[27:28] |OPMODE    |Timer Operating Mode
     * |        |          |00 = The Timer is operating in the one-shot mode.
     * |        |          |The associated interrupt signal is generated once (if INTEN is 1) and CNTEN is automatically cleared by hardware.
     * |        |          |01 = The Timer is operating in the periodic mode.
     * |        |          |The associated interrupt signal is generated periodically (if INTEN is 1).
     * |        |          |10 = Reserved.
     * |        |          |11 = The Timer is operating in continuous counting mode.
     * |        |          |The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is 1); however, the 16-bit up-counter counts continuously without reset.
     * |[29]    |INTEN     |Interrupt Enable Bit
     * |        |          |0 = Disable TIMER Interrupt.
     * |        |          |1 = Enable TIMER Interrupt.
     * |        |          |If timer interrupt is enabled, the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP.
     * |[30]    |CNTEN     |Counter Enable Bit
     * |        |          |0 = Stop/Suspend counting.
     * |        |          |1 = Start counting.
     * |        |          |Note: This bit is auto-cleared by hardware in one-shot mode (OPMODE = 00b) when the associated timer interrupt is generated (INTEN = 1).
     * |[31]    |Reserved_ |Reserved.
 */
    __IO uint32_t CTL;                   

    /**
     * CMP
     * ===================================================================================================
     * Offset: 0x04  Timer Compare Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |CMPDAT    |Timer Comparison Value
     * |        |          |CMPDAT is a 16-bit comparison register.
     * |        |          |When the 16-bit up-counter is enabled and its value is equal to CMPDAT value, a Timer Interrupt is requested if the timer interrupt is enabled with TIMERx_CTL.INTEN = 1.
     * |        |          |Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.
     * |        |          |Note 2: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count.
 */
    __IO uint32_t CMP;                   

    /**
     * INTSTS
     * ===================================================================================================
     * Offset: 0x08  Timer Interrupt Status Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |TIF       |Timer Interrupt Flag (Read Only)
     * |        |          |This bit indicates the interrupt status of Timer.
     * |        |          |TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT).
     * |        |          |It is cleared by writing 1 to itself.
     * |        |          |0 = No effect.
     * |        |          |1 = CNT (TIMERx_CNT[15:0]) value matches the CMPDAT (TIMERx_CMP[15:0]) value. 
 */
    __IO  uint32_t INTSTS;                

    /**
     * CNT
     * ===================================================================================================
     * Offset: 0x0C  Timer Data Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0:15]  |CNT       |Timer Data Register
     * |        |          |User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1, 
 */
    __I  uint32_t CNT;
} TMR_T;

 
typedef struct
{
    /**
     * INTSTS
     * ===================================================================================================
     * Offset: 0x00  TimerF Interrupt Status Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |TFIF      |TimerF Interrupt Flag
     * |        |          |This bit indicates the interrupt status of TimerF.
     * |        |          |TFIF bit is set by hardware when TimerF time out. It is cleared by writing 1 to this bit.
     * |        |          |0 = It indicates that TimerF does not time out yet.
     * |        |          |1 = It indicates that TimerF time out. The interrupt flag is set if TimerF interrupt was enabled.
     * |[1]     |TFIE      |TimerF Interrupt Enable
     * |        |          |0 = Disable TimerF Interrupt.
     * |        |          |1 = Enable TimerF Interrupt.
 */
    __IO uint32_t INTSTS;
} TMRF_T;
 
typedef struct
{
    /**
     * CTL
     * ===================================================================================================
     * Offset: 0x00  IR Carrier Output Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |IRCEN     |IR carrier output enable                                                                
     * |        |          |0 = Disable IR carrier output,                                                          
     * |        |          |1 = Enable IR carrier output. Timer1 time out will toggle the output state on IROUT pin.
     * |[1]     |NONCS     |Non-carrier state                    
     * |        |          |0 = IROUT keeps low when IRCEN is 0, .
     * |        |          |1 = IROUT keeps high when IRCEN is 0.
 */
         uint32_t CTL;
} TMRIR_T;

/**
    @addtogroup TMR_CONST TMR Bit Field Definition
    Constant Definitions for TMR Controller
@{ */

#define TMR_CTL_PSC_Pos                  (0)                                               /*!< TMR CTL: PSC Position                  */
#define TMR_CTL_PSC_Msk                  (0xfful << TMR_CTL_PSC_Pos)                       /*!< TMR CTL: PSC Mask                      */

#define TMR_CTL_ACTSTS_Pos               (25)                                              /*!< TMR CTL: ACTSTS Position               */
#define TMR_CTL_ACTSTS_Msk               (0x1ul << TMR_CTL_ACTSTS_Pos)                     /*!< TMR CTL: ACTSTS Mask                   */

#define TMR_CTL_RSTCNT_Pos               (26)                                              /*!< TMR CTL: RSTCNT Position               */
#define TMR_CTL_RSTCNT_Msk               (0x1ul << TMR_CTL_RSTCNT_Pos)                     /*!< TMR CTL: RSTCNT Mask                   */

#define TMR_CTL_OPMODE_Pos               (27)                                              /*!< TMR CTL: OPMODE Position               */
#define TMR_CTL_OPMODE_Msk               (0x3ul << TMR_CTL_OPMODE_Pos)                     /*!< TMR CTL: OPMODE Mask                   */

#define TMR_CTL_INTEN_Pos                (29)                                              /*!< TMR CTL: INTEN Position                */
#define TMR_CTL_INTEN_Msk                (0x1ul << TMR_CTL_INTEN_Pos)                      /*!< TMR CTL: INTEN Mask                    */

#define TMR_CTL_CNTEN_Pos                (30)                                              /*!< TMR CTL: CNTEN Position                */
#define TMR_CTL_CNTEN_Msk                (0x1ul << TMR_CTL_CNTEN_Pos)                      /*!< TMR CTL: CNTEN Mask                    */

#define TMR_CMP_CMPDAT_Pos               (0)                                               /*!< TMR CMP: CMPDAT Position               */
#define TMR_CMP_CMPDAT_Msk               (0xfffful << TMR_CMP_CMPDAT_Pos)                  /*!< TMR CMP: CMPDAT Mask                   */

#define TMR_INTSTS_TIF_Pos               (0)                                               /*!< TMR INTSTS: TIF Position               */
#define TMR_INTSTS_TIF_Msk               (0x1ul << TMR_INTSTS_TIF_Pos)                     /*!< TMR INTSTS: TIF Mask                   */

#define TMR_CNT_CNT_Pos                  (0)                                               /*!< TMR CNT: CNT Position                  */
#define TMR_CNT_CNT_Msk                  (0xfffful << TMR_CNT_CNT_Pos)                     /*!< TMR CNT: CNT Mask                      */

#define TMR_CTL_PSC_Pos                  (0)                                               /*!< TMR CTL: PSC Position                  */
#define TMR_CTL_PSC_Msk                  (0xfful << TMR_CTL_PSC_Pos)                       /*!< TMR CTL: PSC Mask                      */

#define TMR_CTL_ACTSTS_Pos               (25)                                              /*!< TMR CTL: ACTSTS Position               */
#define TMR_CTL_ACTSTS_Msk               (0x1ul << TMR_CTL_ACTSTS_Pos)                     /*!< TMR CTL: ACTSTS Mask                   */

#define TMR_CTL_RSTCNT_Pos               (26)                                              /*!< TMR CTL: RSTCNT Position               */
#define TMR_CTL_RSTCNT_Msk               (0x1ul << TMR_CTL_RSTCNT_Pos)                     /*!< TMR CTL: RSTCNT Mask                   */

#define TMR_CTL_OPMODE_Pos               (27)                                              /*!< TMR CTL: OPMODE Position               */
#define TMR_CTL_OPMODE_Msk               (0x3ul << TMR_CTL_OPMODE_Pos)                     /*!< TMR CTL: OPMODE Mask                   */

#define TMR_CTL_INTEN_Pos                (29)                                              /*!< TMR CTL: INTEN Position                */
#define TMR_CTL_INTEN_Msk                (0x1ul << TMR_CTL_INTEN_Pos)                      /*!< TMR CTL: INTEN Mask                    */

#define TMR_CTL_CNTEN_Pos                (30)                                              /*!< TMR CTL: CNTEN Position                */
#define TMR_CTL_CNTEN_Msk                (0x1ul << TMR_CTL_CNTEN_Pos)                      /*!< TMR CTL: CNTEN Mask                    */

#define TMR_CMP_CMPDAT_Pos               (0)                                               /*!< TMR CMP: CMPDAT Position               */
#define TMR_CMP_CMPDAT_Msk               (0xfffful << TMR_CMP_CMPDAT_Pos)                  /*!< TMR CMP: CMPDAT Mask                   */

#define TMR_INTSTS_TIF_Pos               (0)                                               /*!< TMR INTSTS: TIF Position               */
#define TMR_INTSTS_TIF_Msk               (0x1ul << TMR_INTSTS_TIF_Pos)                     /*!< TMR INTSTS: TIF Mask                   */

#define TMR_CNT_CNT_Pos                  (0)                                               /*!< TMR CNT: CNT Position                  */
#define TMR_CNT_CNT_Msk                  (0xfffful << TMR_CNT_CNT_Pos)                     /*!< TMR CNT: CNT Mask                      */

#define TMR_INTSTS_TFIF_Pos              (0)                                               /*!< TMR INTSTS: TFIF Position              */
#define TMR_INTSTS_TFIF_Msk              (0x1ul << TMR_INTSTS_TFIF_Pos)                    /*!< TMR INTSTS: TFIF Mask                  */

#define TMR_INTSTS_TFIE_Pos              (1)                                               /*!< TMR INTSTS: TFIE Position              */
#define TMR_INTSTS_TFIE_Msk              (0x1ul << TMR_INTSTS_TFIE_Pos)                    /*!< TMR INTSTS: TFIE Mask                  */

#define TMR_CTL_PSC_Pos                  (0)                                               /*!< TMR CTL: PSC Position                  */
#define TMR_CTL_PSC_Msk                  (0xfful << TMR_CTL_PSC_Pos)                       /*!< TMR CTL: PSC Mask                      */

#define TMR_CTL_ACTSTS_Pos               (25)                                              /*!< TMR CTL: ACTSTS Position               */
#define TMR_CTL_ACTSTS_Msk               (0x1ul << TMR_CTL_ACTSTS_Pos)                     /*!< TMR CTL: ACTSTS Mask                   */

#define TMR_CTL_RSTCNT_Pos               (26)                                              /*!< TMR CTL: RSTCNT Position               */
#define TMR_CTL_RSTCNT_Msk               (0x1ul << TMR_CTL_RSTCNT_Pos)                     /*!< TMR CTL: RSTCNT Mask                   */

#define TMR_CTL_OPMODE_Pos               (27)                                              /*!< TMR CTL: OPMODE Position               */
#define TMR_CTL_OPMODE_Msk               (0x3ul << TMR_CTL_OPMODE_Pos)                     /*!< TMR CTL: OPMODE Mask                   */

#define TMR_CTL_INTEN_Pos                (29)                                              /*!< TMR CTL: INTEN Position                */
#define TMR_CTL_INTEN_Msk                (0x1ul << TMR_CTL_INTEN_Pos)                      /*!< TMR CTL: INTEN Mask                    */

#define TMR_CTL_CNTEN_Pos                (30)                                              /*!< TMR CTL: CNTEN Position                */
#define TMR_CTL_CNTEN_Msk                (0x1ul << TMR_CTL_CNTEN_Pos)                      /*!< TMR CTL: CNTEN Mask                    */

#define TMR_CMP_CMPDAT_Pos               (0)                                               /*!< TMR CMP: CMPDAT Position               */
#define TMR_CMP_CMPDAT_Msk               (0xfffful << TMR_CMP_CMPDAT_Pos)                  /*!< TMR CMP: CMPDAT Mask                   */

#define TMR_INTSTS_TIF_Pos               (0)                                               /*!< TMR INTSTS: TIF Position               */
#define TMR_INTSTS_TIF_Msk               (0x1ul << TMR_INTSTS_TIF_Pos)                     /*!< TMR INTSTS: TIF Mask                   */

#define TMR_CNT_CNT_Pos                  (0)                                               /*!< TMR CNT: CNT Position                  */
#define TMR_CNT_CNT_Msk                  (0xfffful << TMR_CNT_CNT_Pos)                     /*!< TMR CNT: CNT Mask                      */

#define TMRF_INTSTS_TFIF_Pos             (0)                                               /*!< TMRF INTSTS: TIF Position               */
#define TMRF_INTSTS_TFIF_Msk             (0x1ul << TMRF_INTSTS_TFIF_Pos)                   /*!< TMRF INTSTS: TIF Mask                   */

#define TMRF_INTSTS_IFIE_Pos             (1)                                               /*!< TMRF INTSTS: TIE Position               */
#define TMRF_INTSTS_IFIE_Msk             (0x1ul << TMRF_INTSTS_IFIE_Pos)                   /*!< TMRF INTSTS: TIE Mask                   */

#define TMRIR_CTL_IRCEN_Pos              (0)                                               /*!< TMRFIR CTL: IRCEN Position               */
#define TMRIR_CTL_IRCEN_Msk              (0x1ul << TMRIR_CTL_IRCEN_Pos)                    /*!< TMRFIR CTL: IRCEN Mask                   */

#define TMRIR_CTL_NONCS_Pos              (1)                                               /*!< TMRFIR CTL: NONCS Position               */
#define TMRIR_CTL_NONCS_Msk              (0x1ul << TMRIR_CTL_NONCS_Pos)                    /*!< TMRFIR CTL: NONCS Mask                   */

/**@}*/ /* TMR_CONST */
/**@}*/ /* end of TMR register group */


/*---------------------- Watch Dog Timer Controller -------------------------*/
/**
    @addtogroup WDT Watch Dog Timer Controller(WDT)
    Memory Mapped Structure for WDT Controller
@{ */
 
typedef struct
{


    /**
     * CTL
     * ===================================================================================================
     * Offset: 0x00  Watchdog Timer Control Register
     * ---------------------------------------------------------------------------------------------------
     * |Bits    |Field     |Descriptions
     * | :----: | :----:   | :---- |
     * |[0]     |RSTCNT    |Clear Watchdog Timer
     * |        |          |Set this bit will clear the Watchdog timer.
     * |        |          |0 = Writing 0 to this bit has no effect.
     * |        |          |1 = Reset the contents of the Watchdog timer.
     * |        |          |Note: This bit will auto clear after few clock cycles
     * |[1]     |RSTEN     |Watchdog Timer Reset Enable
     * |        |          |Setting this bit will enable the Watchdog timer reset function.
     * |        |          |0 = Disable Watchdog timer reset function.
     * |        |          |1= Enable Watchdog timer reset function.
     * |        |          |Note: This function cannot work with XTL32-based clock source.
     * |[2]     |RSTF      |Watchdog Timer Reset Flag
     * |        |          |When the Watchdog timer initiates a reset, the hardware will set this bit.
     * |        |          |This flag can be read by software to determine the source of reset.
     * |        |          |Software is responsible to clear it manually by writing 1 to it.
     * |        |          |If RSTEN is disabled, then the Watchdog timer has no effect on this bit.
     * |        |          |0 = Watchdog timer reset has not occurred.
     * |        |          |1= Watchdog timer reset has occurred.
     * |        |          |Note: This bit is cleared by writing 1 to this bit.
     * |[3]     |IF        |Watchdog Timer Interrupt Flag
     * |        |          |If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.
     * |        |          |If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
     * |        |          |0 = Watchdog timer interrupt has not occurred.
     * |        |          |1 = Watchdog timer interrupt has occurred.
     * |        |          |Note: This bit is cleared by writing 1 to this bit.
     * |[4]     |WKEN      |WDT Time-Out Wake-Up Function Control
     * |        |          |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
     * |        |          |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
     * |        |          |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
     * |[5]     |WKF       |WDT Time-Out Wake-Up Flag
     * |        |          |If WDT causes CPU wake up from sleep or power-down mode, this bit will be set to high.
     * |        |          |0 = WDT does not cause chip wake-up.
     * |        |          |1 = Chip wakes up from sleep or power-down mode by WDT time-out interrupt.
     * |        |          |Note: This bit is cleared by writing 1 to it. 
     * |[6]     |INTEN     |Watchdog Time-Out Interrupt Enable
     * |        |          |0 = Disable the WDT time-out interrupt.
     * |        |          |1 = Enable the WDT time-out interrupt.
     * |[7]     |WDTEN     |Watchdog Timer Enable
     * |        |          |0 = Disable the WDT(Watchdog timer) (This action will reset the internal counter).
     * |        |          |1 = Enable the WDT(Watchdog timer).
     * |[8:10]  |TOUTSEL   |Watchdog Timer Interval Select
     * |        |          |These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if Watchdog timer is not reset.
     * |        |          |The WDT interrupt timeout is given by:
     * |        |          |000 = 24 * WDT_CLK.
     * |        |          |001 = 26 * WDT_CLK.
     * |        |          |010 = 28 * WDT_CLK.
     * |        |          |011 = 210 * WDT_CLK.
     * |        |          |100 = 212 * WDT_CLK.
     * |        |          |101 = 214 * WDT_CLK.
     * |        |          |110 = 216 * WDT_CLK.
     * |        |          |111 = 218
     * |        |          |* WDT_CLK.
     * |        |          |WDT reset timeout = (WDT interrupt timeout +1024) * WDT_CLK.
     * |        |          |Where WDT_CLK is the period of the Watchdog Timer clock source.
 */
    __IO uint32_t CTL;                   

} WDT_T;

/**
    @addtogroup WDT_CONST WDT Bit Field Definition
    Constant Definitions for WDT Controller
@{ */

#define WDT_CTL_RSTCNT_Pos               (0)                                               /*!< WDT CTL: RSTCNT Position               */
#define WDT_CTL_RSTCNT_Msk               (0x1ul << WDT_CTL_RSTCNT_Pos)                     /*!< WDT CTL: RSTCNT Mask                   */

#define WDT_CTL_RSTEN_Pos                (1)                                               /*!< WDT CTL: RSTEN Position                */
#define WDT_CTL_RSTEN_Msk                (0x1ul << WDT_CTL_RSTEN_Pos)                      /*!< WDT CTL: RSTEN Mask                    */

#define WDT_CTL_RSTF_Pos                 (2)                                               /*!< WDT CTL: RSTF Position                 */
#define WDT_CTL_RSTF_Msk                 (0x1ul << WDT_CTL_RSTF_Pos)                       /*!< WDT CTL: RSTF Mask                     */

#define WDT_CTL_IF_Pos                   (3)                                               /*!< WDT CTL: IF Position                   */
#define WDT_CTL_IF_Msk                   (0x1ul << WDT_CTL_IF_Pos)                         /*!< WDT CTL: IF Mask                       */

#define WDT_CTL_WKEN_Pos                 (4)                                               /*!< WDT CTL: WKEN Position                 */
#define WDT_CTL_WKEN_Msk                 (0x1ul << WDT_CTL_WKEN_Pos)                       /*!< WDT CTL: WKEN Mask                     */

#define WDT_CTL_WKF_Pos                  (5)                                               /*!< WDT CTL: WKF Position                  */
#define WDT_CTL_WKF_Msk                  (0x1ul << WDT_CTL_WKF_Pos)                        /*!< WDT CTL: WKF Mask                      */

#define WDT_CTL_INTEN_Pos                (6)                                               /*!< WDT CTL: INTEN Position                */
#define WDT_CTL_INTEN_Msk                (0x1ul << WDT_CTL_INTEN_Pos)                      /*!< WDT CTL: INTEN Mask                    */

#define WDT_CTL_WDTEN_Pos                (7)                                               /*!< WDT CTL: WDTEN Position                */
#define WDT_CTL_WDTEN_Msk                (0x1ul << WDT_CTL_WDTEN_Pos)                      /*!< WDT CTL: WDTEN Mask                    */

#define WDT_CTL_TOUTSEL_Pos              (8)                                               /*!< WDT CTL: TOUTSEL Position              */
#define WDT_CTL_TOUTSEL_Msk              (0x7ul << WDT_CTL_TOUTSEL_Pos)                    /*!< WDT CTL: TOUTSEL Mask                  */

/**@}*/ /* WDT_CONST */
/**@}*/ /* end of WDT register group */


/**@}*/ /* end of REGISTER group */

/******************************************************************************/
/*                         Peripheral memory map                              */
/******************************************************************************/
/** @addtogroup N572F072_PERIPHERAL_MEM_MAP N572F072 Peripheral Memory Map
  Memory Mapped Structure for N572F072 Series Peripheral
  @{
 */
/* Peripheral and SRAM base address */
#define FLASH_BASE          ((     uint32_t)0x00000000)
#define SRAM_BASE           ((     uint32_t)0x20000000)
#define AHB_BASE            ((     uint32_t)0x50000000)
#define APB1_BASE           ((     uint32_t)0x40000000)

/* Peripheral memory map */
/******************************************************************************/
/*						   Peripheral memory map							  */
/******************************************************************************/

#define WDT_BASE       	     (APB1_BASE      + 0x04000)
#define RTC_BASE             (APB1_BASE      + 0x08000)
#define TIMER0_BASE          (APB1_BASE      + 0x10000)
#define TIMER1_BASE          (APB1_BASE      + 0x10020)
#define	TIMERF_BASE          (APB1_BASE      + 0x10030)
#define	TIMERIR_BASE         (APB1_BASE      + 0x10034)
#define	TIMER2_BASE          (APB1_BASE      + 0x10040)
#define SPI0_BASE            (APB1_BASE      + 0x30000)
#define SPI1_BASE            (APB1_BASE      + 0x34000)
#define PWM_BASE             (APB1_BASE      + 0x40000)
#define	ADC_BASE             (APB1_BASE      + 0xE0000)


#define SYS_BASE             (AHB_BASE       + 0x00000)
#define CLK_BASE             (AHB_BASE       + 0x00200)
#define GPIO_BASE            (AHB_BASE       + 0x04000)
#define GPIOA_BASE           (GPIO_BASE               )
#define GPIOB_BASE           (GPIO_BASE      + 0x00040)
#define	APU_BASE             (AHB_BASE       + 0x08000)
#define FMC_BASE             (AHB_BASE       + 0x0C000)

/*@}*/ /* end of group N572F072_PERIPHERAL_MEM_MAP */
/******************************************************************************/
/*                         Peripheral declaration                             */
/******************************************************************************/
/** @addtogroup N572F072_PeripheralDecl N572F072 Peripheral Declaration
    @{
*/
#define WDT                 ((WDT_T *) WDT_BASE)
#define RTC                 ((RTC_T *) RTC_BASE)
#define TIMER0              ((TMR_T *) TIMER0_BASE)
#define TIMER1              ((TMR_T *) TIMER1_BASE)
#define TIMERF              ((TMRF_T *) TIMERF_BASE)
#define TIMER_IR            ((TMRIR_T *) TIMERIR_BASE)
#define TIMER2              ((TMR_T *) TIMER2_BASE)
#define SPI0                ((SPI_T *) SPI0_BASE)
#define SPI1                ((SPI_T *) SPI1_BASE)
#define PWM                 ((PWM_T *) PWM_BASE)
#define ADC                 ((ADC_T*)  ADC_BASE)

#define SYS                 ((SYS_T *) SYS_BASE)
#define CLK                 ((CLK_T *) CLK_BASE)
#define PA                  ((GPIO_T *) GPIOA_BASE)
#define PB                  ((GPIO_T *) GPIOB_BASE)
#define APU					((APU_T *) APU_BASE)
#define FMC                 ((FMC_T *) FMC_BASE)

/*@}*/ /* end of group N572F072_PeripheralDecl */

#define UNLOCKREG(x)        do{*((__IO uint32_t *)(SYS_BASE + 0x100)) = 0x59;*((__IO uint32_t *)(SYS_BASE + 0x100)) = 0x16;*((__IO uint32_t *)(SYS_BASE + 0x100)) = 0x88;}while(*((__IO uint32_t *)(SYS_BASE + 0x100))==0)
#define LOCKREG(x)          *((__IO uint32_t *)(SYS_BASE + 0x100)) = 0x00

#define REGCOPY(dest, src)  *((uint32_t *)&(dest)) = *((uint32_t *)&(src))
#define CLEAR(dest)         *((uint32_t *)&(dest)) = 0

//=============================================================================
/** @addtogroup N572F072_IO_ROUTINE N572F072 I/O routines
  The Declaration of N572F072 I/O routines
  @{
 */

typedef volatile unsigned char  vu8;        ///< Define 8-bit unsigned volatile data type
typedef volatile unsigned short vu16;       ///< Define 16-bit unsigned volatile data type
typedef volatile unsigned long  vu32;       ///< Define 32-bit unsigned volatile data type

/**
  * @brief Get a 8-bit unsigned value from specified address
  * @param[in] addr Address to get 8-bit data from
  * @return  8-bit unsigned value stored in specified address
  */
#define M8(addr)  (*((vu8  *) (addr)))

/**
  * @brief Get a 16-bit unsigned value from specified address
  * @param[in] addr Address to get 16-bit data from
  * @return  16-bit unsigned value stored in specified address
  * @note The input address must be 16-bit aligned
  */
#define M16(addr) (*((vu16 *) (addr)))

/**
  * @brief Get a 32-bit unsigned value from specified address
  * @param[in] addr Address to get 32-bit data from
  * @return  32-bit unsigned value stored in specified address
  * @note The input address must be 32-bit aligned
  */
#define M32(addr) (*((vu32 *) (addr)))

/**
  * @brief Set a 32-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 32-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  * @note The output port must be 32-bit aligned
  */
#define outpw(port,value)     *((volatile unsigned int *)(port)) = value

/**
  * @brief Get a 32-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 32-bit data from
  * @return  32-bit unsigned value stored in specified I/O port
  * @note The input port must be 32-bit aligned
  */
#define inpw(port)            (*((volatile unsigned int *)(port)))

/**
  * @brief Set a 16-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 16-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  * @note The output port must be 16-bit aligned
  */
#define outps(port,value)     *((volatile unsigned short *)(port)) = value

/**
  * @brief Get a 16-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 16-bit data from
  * @return  16-bit unsigned value stored in specified I/O port
  * @note The input port must be 16-bit aligned
  */
#define inps(port)            (*((volatile unsigned short *)(port)))

/**
  * @brief Set a 8-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 8-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  */
#define outpb(port,value)     *((volatile unsigned char *)(port)) = value

/**
  * @brief Get a 8-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 8-bit data from
  * @return  8-bit unsigned value stored in specified I/O port
  */
#define inpb(port)            (*((volatile unsigned char *)(port)))

/**
  * @brief Set a 32-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 32-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  * @note The output port must be 32-bit aligned
  */
#define outp32(port,value)    *((volatile unsigned int *)(port)) = value

/**
  * @brief Get a 32-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 32-bit data from
  * @return  32-bit unsigned value stored in specified I/O port
  * @note The input port must be 32-bit aligned
  */
#define inp32(port)           (*((volatile unsigned int *)(port)))

/**
  * @brief Set a 16-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 16-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  * @note The output port must be 16-bit aligned
  */
#define outp16(port,value)    *((volatile unsigned short *)(port)) = value

/**
  * @brief Get a 16-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 16-bit data from
  * @return  16-bit unsigned value stored in specified I/O port
  * @note The input port must be 16-bit aligned
  */
#define inp16(port)           (*((volatile unsigned short *)(port)))

/**
  * @brief Set a 8-bit unsigned value to specified I/O port
  * @param[in] port Port address to set 8-bit data
  * @param[in] value Value to write to I/O port
  * @return  None
  */
#define outp8(port,value)     *((volatile unsigned char *)(port)) = value

/**
  * @brief Get a 8-bit unsigned value from specified I/O port
  * @param[in] port Port address to get 8-bit data from
  * @return  8-bit unsigned value stored in specified I/O port
  */
#define inp8(port)            (*((volatile unsigned char *)(port)))

/*@}*/ /* end of group N572F072_IO_ROUTINE */




/** @addtogroup N572F072_legacy_Constants N572F072 Legacy Constants
  N572F072 Legacy Constants
  @{
*/


#define E_SUCCESS   0
#ifndef NULL
#define NULL        0
#endif

#define TRUE        1
#define FALSE       0

#define ENABLE     1
#define DISABLE    0

/* Define one bit mask */
#define BIT0    0x00000001
#define BIT1    0x00000002
#define BIT2    0x00000004
#define BIT3    0x00000008
#define BIT4    0x00000010
#define BIT5    0x00000020
#define BIT6    0x00000040
#define BIT7    0x00000080
#define BIT8    0x00000100
#define BIT9    0x00000200
#define BIT10   0x00000400
#define BIT11   0x00000800
#define BIT12   0x00001000
#define BIT13   0x00002000
#define BIT14   0x00004000
#define BIT15   0x00008000
#define BIT16   0x00010000
#define BIT17   0x00020000
#define BIT18   0x00040000
#define BIT19   0x00080000
#define BIT20   0x00100000
#define BIT21   0x00200000
#define BIT22   0x00400000
#define BIT23   0x00800000
#define BIT24   0x01000000
#define BIT25   0x02000000
#define BIT26   0x04000000
#define BIT27   0x08000000
#define BIT28   0x10000000
#define BIT29   0x20000000
#define BIT30   0x40000000
#define BIT31   0x80000000

/* Byte Mask Definitions */
#define BYTE0_Msk               (0x000000FF)
#define BYTE1_Msk               (0x0000FF00)
#define BYTE2_Msk               (0x00FF0000)
#define BYTE3_Msk               (0xFF000000)

#define _GET_BYTE0(u32Param)    ((u32Param & BYTE0_Msk)      )  /*!< Extract Byte 0 (Bit  0~ 7) from parameter u32Param */
#define _GET_BYTE1(u32Param)    ((u32Param & BYTE1_Msk) >>  8)  /*!< Extract Byte 1 (Bit  8~15) from parameter u32Param */
#define _GET_BYTE2(u32Param)    ((u32Param & BYTE2_Msk) >> 16)  /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define _GET_BYTE3(u32Param)    ((u32Param & BYTE3_Msk) >> 24)  /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */

/*@}*/ /* end of group N572F072_legacy_Constants */

/*@}*/ /* end of group N572F072_Definitions */

#define __N572F072_SERIES__ (0x05720072)
#define __CHIP_SERIES__ __N572F072_SERIES__
/******************************************************************************/
/*                         Peripheral header files                            */
/******************************************************************************/
#include "sys.h"
#include "clk.h"
#include "gpio.h"
#include "timer.h"
#include "pwm.h"
#include "fmc.h"
#include "wdt.h"
#include "rtc.h"
#include "spi.h"
#include "apu.h"
#include "adc.h"

#endif	// __N572F072_H__

