/**************************************************************************//**
 * @file     clk.h
 * @version  V1.00
 * $Revision: 6$
 * $Date: 14/06/23 2:35p $
 * @brief    N572 series CLK driver header file
 *
 * @note
 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CLK_H__
#define __CLK_H__

#ifdef __cplusplus
extern "C"
{
#endif

/** @addtogroup N572_Device_Driver N572 Device Driver
  @{
*/

/** @addtogroup N572_CLK_Driver CLK Driver
  @{
*/

/** @addtogroup N572_CLK_EXPORTED_CONSTANTS CLK Exported Constants
  @{
*/

#if( __CHIP_SERIES__ == __N572F065_SERIES__ )

#define _PLL_STABLE_COUNT_		500000 		// about 100ms count on CPU run 24MHz to wait PLL stable

// PLL2 Clock Source constant definitions.	
#define PLL2_SRC_XTL_6M  (0<<CLK_PLLCON_PLL_SRC_Pos)
#define PLL2_SRC_PLL1_FOUT (1<<CLK_PLLCON_PLL_SRC_Pos)
#define PLL2_SRC_XTL_12M (2<<CLK_PLLCON_PLL_SRC_Pos)

// CLKSEL0 constant definitions.  (Write-protection)
#define CLK_CLKSEL0_HCLKSEL_XTL_32K      (0x000UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_XTL_12M_6M   (0x001UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as XTAL 12M/6M  \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_PLL1_FOUT    (0x002UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL1  \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_PLL2_FOUT    (0x004UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL2  \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_RC_24M       (0x007UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as 24MHz RC clock  \hideinitializer */

// CLKSEL1 constant definitions.
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048  (0x0UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as HCLK/2048  \hideinitializer */
#define CLK_CLKSEL1_WDTSEL_XTL_32K       (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL1_WDTSEL_XTL_12M_6M    (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as XTAL 12M/6M  \hideinitializer */
#define CLK_CLKSEL1_WDTSEL_RC_24M        (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as 24MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_ADCSEL_PLL2_FOUT     (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting WDT clock source as PLL2 \hideinitializer */
#define CLK_CLKSEL1_ADCSEL_XTL_12M_6M    (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting WDT clock source as XTAL 12M/6M  \hideinitializer */
#define CLK_CLKSEL1_ADCSEL_RC_24M        (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting WDT clock source as 24MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_TMR0SEL_HCLK         (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)      /*!< Setting Timer 0 clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_XTL_32K      (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)      /*!< Setting Timer 0 clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_XTL_12M_6M   (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos)      /*!< Setting Timer 0 clock source as XTAL 12M/6M  \hideinitializer */    
#define CLK_CLKSEL1_TMR0SEL_EXT          (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)      /*!< Setting Timer 0 clock source as external trigger  \hideinitializer */    
#define CLK_CLKSEL1_TMR0SEL_RC_24M       (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos)      /*!< Setting Timer 0 clock source as 24MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_TMR1SEL_HCLK         (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_XTL_32K      (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_XTL_12M_6M   (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as XTAL 12M/6M  \hideinitializer */    
#define CLK_CLKSEL1_TMR1SEL_EXT          (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as external trigger  \hideinitializer */    
#define CLK_CLKSEL1_TMR1SEL_RC_24M       (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as 24MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_TMR2SEL_HCLK         (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_XTL_32K      (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_XTL_12M_6M   (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as XTAL 12M/6M  \hideinitializer */    
#define CLK_CLKSEL1_TMR2SEL_EXT          (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as external trigger  \hideinitializer */    
#define CLK_CLKSEL1_TMR2SEL_RC_24M       (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as 24MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_TMRFSEL_XTL_32K_DIV32         		(0x0UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as XTAL_32K/32  \hideinitializer */
#define CLK_CLKSEL1_TMRFSEL_XTL_32K_DIV128       			(0x1UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as XTAL_32K/128  \hideinitializer */
#define CLK_CLKSEL1_TMRFSEL_XTL_12M_6M_DIV16384       (0x2UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as XTAL_12M_8M/16384  \hideinitializer */
#define CLK_CLKSEL1_TMRFSEL_XTL_12M_6M_DIV16384_DIV4  (0x3UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as XTAL_12M_6M/16384/4  \hideinitializer */
#define CLK_CLKSEL1_TMRFSEL_RC_24M_DIV32768       		(0x6UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as 24M/32768  \hideinitializer */
#define CLK_CLKSEL1_TMRFSEL_RC_24M_DIV32768_DIV4  		(0x7UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as 24M/32768/4  \hideinitializer */    

#define CLK_CLKSEL1_PWMSEL_HCLK         (0x0UL<<CLK_CLKSEL1_PWMSEL_Pos)   /*!< Setting PWM0 and PWM clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_PWMSEL_XTL_32K      (0x1UL<<CLK_CLKSEL1_PWMSEL_Pos)   /*!< Setting PWM0 and PWM clock source as XTAL_32K  \hideinitializer */
#define CLK_CLKSEL1_PWMSEL_XTL_12M_6M   (0x2UL<<CLK_CLKSEL1_PWMSEL_Pos)   /*!< Setting PWM0 and PWM clock source as XTAL_12M_6M  \hideinitializer */
#define CLK_CLKSEL1_PWMSEL_RC_24M       (0x3UL<<CLK_CLKSEL1_PWMSEL_Pos)   /*!< Setting PWM0 and PWM clock source as 24MHz RC clock  \hideinitializer */

// AHBCLK/APBCLK(1) | CLKSEL(1) | CLKSEL_Msk(3) |    CLKSEL_Pos(5)    | CLKDIV(0) | CLKDIV_Msk(12) |     CLKDIV_Pos(5)  |  IP_EN_Pos(5)
#define ISP_MODULE       ((0UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISPCKEN_Pos)   /*!< ISP Module  \hideinitializer */
#define WDT_MODULE       ((1UL<<31)|(1<<30)|(           3<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos)    /*!< Watchdog Timer Module  \hideinitializer */
#define RTC_MODULE       ((1UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos)    /*!< RTC Module  \hideinitializer */
#define TMR0_MODULE      ((1UL<<31)|(1<<30)|(           7<<27)|( 8<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_TMR0_EN_Pos)   /*!< Timer0 Module  \hideinitializer */
#define TMR1_MODULE      ((1UL<<31)|(1<<30)|(           7<<27)|(12<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_TMR1_EN_Pos)   /*!< Timer1 Module  \hideinitializer */
#define TMR2_MODULE      ((1UL<<31)|(1<<30)|(           7<<27)|(16<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_TMR2_EN_Pos)   /*!< Timer2 Module  \hideinitializer */
#define TMRF_MODULE      ((1UL<<31)|(1<<30)|(           7<<27)|(20<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_TMRF_EN_Pos)   /*!< TimerF Module  \hideinitializer */
#define SPI0_MODULE      ((1UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos)   /*!< SPI0 Module  \hideinitializer */
#define SPI1_MODULE      ((1UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos)   /*!< SPI1 Module  \hideinitializer */
#define PWM_MODULE       ((1UL<<31)|(1<<30)|(           3<<27)|(28<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM_EN_Pos)    /*!< PWM Module  \hideinitializer */
#define USBD_MODULE      ((1UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_USBD_EN_Pos)   /*!< USBD Module  \hideinitializer */
#define ADC_MODULE       ((1UL<<31)|(1<<30)|(           3<<27)|( 2<<22)|(0<<22)|(       0xFFF<<10)|(16<<5)|CLK_APBCLK_ADC_EN_Pos)    /*!< ADC Module  \hideinitializer */
#define APU_MODULE       ((1UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_APU_EN_Pos)    /*!< APU Module  \hideinitializer */
	
#endif

#if( __CHIP_SERIES__ == __N572F072_SERIES__ )

#define _PLL_STABLE_COUNT_		500000/2	// about 100ms count on CPU run 12MHz(default when power up or reset) to wait PLL stable

// PLL2 Clock Source constant definitions.
#define PLL2_SRC_RC_48M    (0<<CLK_PLLCON_PLL2_SRC_Pos)
#define PLL2_SRC_PLL1_FOUT (1<<CLK_PLLCON_PLL2_SRC_Pos)

// PLL2 Clock Frequence constant definitions.
#define PLL2_30M (0x00<<CLK_PLLCON_PLL2_FRQ_Pos)
#define PLL2_36M (0x01<<CLK_PLLCON_PLL2_FRQ_Pos)
#define PLL2_42M (0x02<<CLK_PLLCON_PLL2_FRQ_Pos)
#define PLL2_48M (0x03<<CLK_PLLCON_PLL2_FRQ_Pos)

// CLKSEL0 constant definitions.  (Write-protection)
#define CLK_CLKSEL0_HCLKSEL_XTL_32K      (0x000UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_PLL1_FOUT    (0x002UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL1  \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_PLL2_FOUT    (0x004UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL2  \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_RC_48M       (0x007UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as 48MHz RC clock  \hideinitializer */
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2   (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos)  /*!< Setting clock source as HCLK/2  \hideinitializer */
#define CLK_CLKSEL0_STCLKSEL_XTL_32K     (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos)  /*!< Setting clock source as XTAL 32.768KHz  \hideinitializer */

// CLKSEL1 constant definitions.
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048  (0x0UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as HCLK/2048  \hideinitializer */
#define CLK_CLKSEL1_WDTSEL_XTL_32K       (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL1_WDTSEL_PLL1_FOUT     (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as PLL1  \hideinitializer */
#define CLK_CLKSEL1_WDTSEL_RC_48M        (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)       /*!< Setting WDT clock source as 48MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_ADCSEL_PLL2_FOUT     (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting WDT clock source as PLL2 \hideinitializer */
#define CLK_CLKSEL1_ADCSEL_HCLK          (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting WDT clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_ADCSEL_RC_48M        (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos)       /*!< Setting WDT clock source as 48MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_SPI0SEL_HCLK         (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos)       /*!< Setting WDT clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_SPI0SEL_PLL2_FOUT    (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos)       /*!< Setting WDT clock source as PLL2  \hideinitializer */
#define CLK_CLKSEL1_SPI0SEL_RC_48M       (0x3UL<<CLK_CLKSEL1_SPI0SEL_Pos)       /*!< Setting WDT clock source as 48MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_TMR0SEL_HCLK         (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)      /*!< Setting Timer 0 clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_XTL_32K      (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)      /*!< Setting Timer 0 clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_EXT          (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)      /*!< Setting Timer 0 clock source as external trigger  \hideinitializer */    
#define CLK_CLKSEL1_TMR0SEL_RC_48M       (0x4UL<<CLK_CLKSEL1_TMR0SEL_Pos)      /*!< Setting Timer 0 clock source as 48MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_TMR1SEL_HCLK         (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_XTL_32K      (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_EXT          (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as external trigger   \hideinitializer */    
#define CLK_CLKSEL1_TMR1SEL_RC_48M       (0x4UL<<CLK_CLKSEL1_TMR1SEL_Pos)      /*!< Setting Timer 1 clock source as 48MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_TMR2SEL_HCLK         (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_XTL_32K      (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as XTAL 32.768KHz  \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_EXT          (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as external trigger   \hideinitializer */    
#define CLK_CLKSEL1_TMR2SEL_RC_48M       (0x4UL<<CLK_CLKSEL1_TMR2SEL_Pos)      /*!< Setting Timer 2 clock source as 48MHz RC clock  \hideinitializer */

#define CLK_CLKSEL1_TMRFSEL_XTL_32K_DIV32         (0x0UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as XTAL/32  \hideinitializer */
#define CLK_CLKSEL1_TMRFSEL_XTL_32K_DIV128        (0x1UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as XTAL/128  \hideinitializer */
#define CLK_CLKSEL1_TMRFSEL_RC_48M_DIV65536       (0x6UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as 48M/65536  \hideinitializer */
#define CLK_CLKSEL1_TMRFSEL_RC_48M_DIV65536_DIV4  (0x7UL<<CLK_CLKSEL1_TMRFSEL_Pos)      /*!< Setting Timer F clock source as 48M/65536/4  \hideinitializer */    

#define CLK_CLKSEL1_PWMSEL_HCLK         (0x0UL<<CLK_CLKSEL1_PWMSEL_Pos)   /*!< Setting PWM0 and PWM clock source as HCLK  \hideinitializer */
#define CLK_CLKSEL1_PWMSEL_XTL_32K      (0x1UL<<CLK_CLKSEL1_PWMSEL_Pos)   /*!< Setting PWM0 and PWM clock source as XTAL  \hideinitializer */
#define CLK_CLKSEL1_PWMSEL_RC_48M       (0x3UL<<CLK_CLKSEL1_PWMSEL_Pos)   /*!< Setting PWM0 and PWM clock source as 48MHz RC clock  \hideinitializer */

// AHBCLK/APBCLK(1) | CLKSEL(1) | CLKSEL_Msk(3) |    CLKSEL_Pos(5)    | CLKDIV(0) | CLKDIV_Msk(12) |     CLKDIV_Pos(5)  |  IP_EN_Pos(5)
#define ISP_MODULE       ((0UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISPCKEN_Pos)   /*!< ISP Module  \hideinitializer */
#define APU_MODULE       ((0UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_APUCKEN_Pos)   /*!< APU Module  \hideinitializer */
#define WDT_MODULE       ((1UL<<31)|(1<<30)|(           3<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos)    /*!< Watchdog Timer Module  \hideinitializer */
#define RTC_MODULE       ((1UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos)    /*!< RTC Module  \hideinitializer */
#define TMR0_MODULE      ((1UL<<31)|(1<<30)|(           7<<27)|( 8<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_TMR0_EN_Pos)   /*!< Timer0 Module  \hideinitializer */
#define TMR1_MODULE      ((1UL<<31)|(1<<30)|(           7<<27)|(12<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_TMR1_EN_Pos)   /*!< Timer1 Module  \hideinitializer */
#define TMR2_MODULE      ((1UL<<31)|(1<<30)|(           7<<27)|(16<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_TMR2_EN_Pos)   /*!< Timer2 Module  \hideinitializer */
#define TMRF_MODULE      ((1UL<<31)|(1<<30)|(           7<<27)|(20<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_TMRF_EN_Pos)   /*!< TimerF Module  \hideinitializer */
#define SPI0_MODULE      ((1UL<<31)|(1<<30)|(           3<<27)|( 4<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos)   /*!< SPI0 Module  \hideinitializer */
#define SPI1_MODULE      ((1UL<<31)|(0<<30)|(MODULE_NoMsk<<27)|( 0<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos)   /*!< SPI1 Module  \hideinitializer */
#define PWM_MODULE       ((1UL<<31)|(1<<30)|(           3<<27)|(28<<22)|(0<<22)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM_EN_Pos)    /*!< PWM Module  \hideinitializer */
#define ADC_MODULE       ((1UL<<31)|(1<<30)|(           3<<27)|( 2<<22)|(0<<22)|(       0xFFF<<10)|(16<<5)|CLK_APBCLK_ADC_EN_Pos)    /*!< ADC Module  \hideinitializer */
	
#endif

// PLL2 mode constant definitions.
#define PLL_NORMAL_MODE    0
#define PLL_PWOERDOWN_MODE 1

// CLKDIV constant definitions.
#define CLK_CLKDIV_HCLK(x)    (((x)-1) << CLK_CLKDIV_HCLKDIV_Pos)    /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16  \hideinitializer */
#define CLK_CLKDIV_ADC(x)     (((x)-1) << CLK_CLKDIV_ADCDIV_Pos)     /*!< CLKDIV Setting for ADC clock divider. It could be 1~4096  \hideinitializer */

// MODULE constant definitions.
#define MODULE_AHPBCLK(x)                  ((x >>31) & 0x1)    /*!< Calculate AHBCLK/APBCLK offset on MODULE index  \hideinitializer */
#define MODULE_CLKSEL(x)                   ((x >>30) & 0x1)    /*!< Calculate CLKSEL0~1 register offset by MODULE index  \hideinitializer */
#define MODULE_CLKSEL_Msk(x)               ((x >>27) & 0x7)    /*!< Calculate mask bits of CLKSEL0~1 by MODULE index  \hideinitializer */
#define MODULE_CLKSEL_Pos(x)               ((x >>22) & 0x1f)   /*!< Calculate mask bits offset of CLKSEL0~1 by MODULE index  \hideinitializer */
#define MODULE_CLKDIV(x)                   ((x >>22) & 0x0)    /*!< Calculate APBCLK CLKDIV by MODULE index  \hideinitializer */
#define MODULE_CLKDIV_Msk(x)               ((x >>10) & 0xfff)  /*!< Calculate mask bits of CLKDIV by MODULE index  \hideinitializer */
#define MODULE_CLKDIV_Pos(x)               ((x >>5 ) & 0x1f)   /*!< Calculate ask bits offset of CLKDIV by MODULE index  \hideinitializer */
#define MODULE_IP_EN_Pos(x)                ((x >>0 ) & 0x1f)   /*!< Calculate APBCLK enabled offset by MODULE index  \hideinitializer */
#define MODULE_NoMsk                       0x0                 /*!< Not mask by MODULE index  \hideinitializer */

/*@}*/ /* end of group N572_CLK_EXPORTED_CONSTANTS */


/** @addtogroup N572_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
  @{
*/

/**
  * @brief     Get power down state.
  * @param[in] clk Base address of CLK module.
  * @param[in] u8Flag Power state flag.
  *            - \ref CLK_PWRCTL_PD_WAIT_CPU_Msk
  *            - \ref CLK_PWRCTL_PWR_DOWN_Msk
  *            - \ref CLK_PWRCTL_WINT_STS_Msk
  *            - \ref CLK_PWRCTL_WINT_EN_Msk
  * @return    power down flag
  */
#define CLK_GET_POWERDOWNFLAG(clk, u8Flag)		(clk->PWRCTL&u8Flag)

void CLK_SetPLL1Mode(uint32_t u32PllMode);
void CLK_SetPLL2Mode(uint32_t u32PllMode);
void CLK_EnablePowerDownMode(void);
void CLK_DisablePowerDownMode(void);
void CLK_ClearWakeUpStatusFlag(void);
void CLK_EnableWakeUpInterrupt(void);
void CLK_DisableWakeUpInterrupt(void);
void CLK_EnableWakeUpDelay(void);
void CLK_DisableWakeUpDelay(void);
void CLK_EnableLDO30(void);
void CLK_DisableLDO30(void);
uint32_t CLK_GetHCLKFreq(void);
void CLK_SetPLL2(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
uint32_t CLK_GetPLL2ClockFreq(void);
void CLK_EnableXtalRC(uint32_t u32ClkMask);
void CLK_DisableXtalRC(uint32_t u32ClkMask);
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);

#if( __CHIP_SERIES__ == __N572F072_SERIES__ )
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
void CLK_SysTickDelay(uint32_t us);
#endif

/*@}*/ /* end of group N572_CLK_EXPORTED_FUNCTIONS */

/*@}*/ /* end of group N572_CLK_Driver */

/*@}*/ /* end of group N572_Device_Driver */

#ifdef __cplusplus
}
#endif

#endif //__CLK_H__

/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
